explain or define difference between analog to digital converter and digital to analog converter meaning definition ?

**Digital System **

**Digital system **A digital system is a data technology that uses disctete (discontinuous values. by contrast, analog (non-digital) systems use a continuous range of values of represent information.

**Analog to Digital Converter and Digital to Analog Converter**

The circuit that converts the analog to digital form is called analog to digital converter (ADC).

The circuit that converters the binary input into its equivalent analog voltage or current is called digital to analog converter (DAC).

Both ADC and DAC are also known as data converters and are avilable in IC form.

**Digital to Analog Converter**

D/A conversion is a process of taking a value represented in digital code and converting to a voltage or current which is proportional to the digital value. the schematic of a DAC is shown in figure.

The input is an n bit binary word D and is combined with reference voltage V_{R} to give an analog output signal. the output of a D/A converter is mathematically described as

V_{O} = KV_{FS} (d_{1}2^{-1} + d_{2}2^{-2} + ….+ d_{n} 2^{-n} ) …….(1)

where, V_{O} = output voltage

V_{FS} = full scale output voltage

K = scaling factor usually adjusted to unity

d_{1}, d_{2} …….., d_{n} = n-bit binary fractional word with the decimal point located at the left

d_{1} = MSB with a weight of V_{FS}/2

d_{n} = LSB with a weight of V_{FS} /2^{N}

The following are resistive techniques used in DAC :

- Weighted resistor DAC
- R-2R ladder DAC
**Weighted Resistor DAC**

Weighted resistor DAC uses a summing amplifier with a binary weighted resistor network. it has n-electronic switches d_{1}, d_{2}, …….. , d_{n} controlled by input word.

**Expression for Analog output Voltage**

The output current I_{O} can be expressed as the sum of individual currents through the weighted resistors

I_{O} = I_{1} + I_{2} + I_{3} + ……+ I_{N}

I_{O} = V_{R}/2R d_{1} + V_{R}/2^{2}R d_{2} + V_{R}/2^{3}R d_{3} + …. + V_{N}/2^{N}R d_{n}

here, d_{1}, d_{2}, ………, d_{n} having values 0 or 1.

I_{O} = V_{R}/R [d_{1}2^{-1} + d_{2}2^{-2} + …..+ d_{n}2^{-n}] ……………(2)

and the output voltage V_{O} is given by

V_{O} = I_{O}R_{F} = V_{R} R_{F}/R [d_{1}2^{-1} + d_{2}2^{-2} + ……+ d_{n} 2^{-n}] …………(3)

now, comparing Eq. (1) from Eq. (3),

K = R_{F}/R and V_{FS} = V_{R}

IF R_{F} = R then, K = 1

But substituting the values of d_{1}, d_{2},………, d_{n} we can obtain the corresponding analog output voltage V_{O}.

**Output Voltage Waveform of a 3-bit DAC**

output voltage

V_{O } = V_{R} R_{F}/R [d_{1}2^{-1} + d_{2}2^{-2} +………….+ d_{n} 2^{-n}]

for 3-bit DAC, putting R_{F}/F = K = 1

V_{O} = V_{R} [d_{1}2^{-1} + d_{2} 2^{-2} + d_{3 }2^{-3}]

Substituting the values of d_{1}, d_{2} and d_{3} into the above equation, we get equivalent analog output voltage V_{O}.

**Example 1. **An 8-bit digital data 10101100 is fed to an ADC. the reference voltage is + 10 V. what will be the analog output voltage ?

**Sol.** output voltage is

V_{O} = V_{R} [2^{-1} d_{1} + 2^{-2} d_{2} + ………+ 2^{-n} d_{n}]

or V_{O} = V_{R}/2^{N} – 1 [2^{N-1} d_{n-1} + 2^{n-2} d_{n-2} + ……+ d_{o}]

= 10/2^{8} – 1 [(1 x 128) + (0 x 64) + (1 x 32) + (0 x 16) + (1 x 8) + (1 x 4) + (0 x 2) + (0 x 1)]

= 10/255 x 172

= 6.74 V

**R-2R Ladder**

Wide range of resistors are required in binary weighted resistor. this problem arises in binary weighted resistor. DAC is eliminated by using R-2R ladder.

Only two types of resistor are used, i.e., R and 2R. the staircase voltage is more likely to be monotonic as the effect of the MSB resistor is not many times greater than that for LSB resistor. the output voltage V_{O} is given by

V_{O} = – R_{F}/3R . V_{R} ^{N-1}/2^{N} ^{i=0} d_{i}2^{i}

= – 3R/3R x 5/16 [0 x 2^{3} + 1 x 2^{2} + 1 x 2 + 0 x 2^{0}

= – 5/16 (4 + 2)

= -5 + 6/16

V_{0} = – 1.88 V

**DAC Specifications**

There are several parameters which are used to describe the characteristics of a D/A converter. some of these include

(i) resolution

(ii) accuracy

(iii) linearity

(iv) temperature sensitivity

(v) offset error

(vi) settling time

(vii) monotonicity

**(i) Resolution**

The resolution of a DAC is defined as the smallest change that can occur in the analog output as a result of a change in the digital input. the resolution always equal to the weight of LSB and is also referred to as step size.

For an N-bit DAC, the number of different levels or steps will be 2^{n} – 1. therefore,

Step size or resolution

Full scale output/Number of steps = V_{FS}/2^{N} – 1

Resolution can also be expressed as

Resolution = 2^{n}

Resolution can be expressed as the amount of voltage or current per step. it is also useful to express it as a percentage of full scale output.

resolution = step size/full scale output x 100 = 1/2^{n} – 1 x 100

**Example 3. **What is per cent resolution of a 8-bit BCD D/A converter ?

**Sol. **percentage resolution = 1/2^{n} – 1 x 100

N = 8

Percentage resolution = 1/2^{8}-1 x 100

= 1/256 – 1 x 100

= 1/255 x 100 = 0.39 %

**(ii) Accuracy**

Accuracy is the maximum deviation of the DACs output from its expected value. it is the measure of difference between the actual analog output voltage to the expected output value. it is expressed as percentage of full scale.

**Example 4. **A D/A converter had 5 v full scale output voltage and an accuracy of + 0.2% what will be the maximum error for any output voltage?

**Sol. ** full scale output voltage = 5 v

accuracy = 0.2%

maximum error in output = 5 x 0.2 /100 = 1/100 = 0.01 v

this means that the output of this DAC can at any instant be off by as much as 0.01 v from its expected value.

**(iii) Linearity**

The relation between the digital input and analog output should be linear.

**(iv) Temperature sensitivity**

The analog output voltage of a DAC varies with temperature for any fixed digital input. change in the output with temperature referred to as temperature sensitivity.

**(v) Settling time**

Settling time is the time required foe DAC output to go from zero to full scale. theoretically, the analog output voltage should change instantly in response to change in its digital input.

**(vi) Offset error**

The output of a DAC will be ideally zero volts when the binary inputs is all 0’s. but practically the output voltage is not zero. but there is always a small voltage present in the output for this situation. this is known as the offset error.

**(vii) Monotonicity**

A DAC is monotonic, if its output increases as the binary input incremented from one value to other.

**Analog to Digital Converters**

An analog to digital converter takes an analog input voltage and converters into the equivalent digital output the analog to digital conversion process is more complex and time consuming than the DAC process.

Following are the different methods used for analog to digital conversion :

(i) Digital ramp A/D converter

(ii) Single slope A/D converter

(iii) Dual slope A/D converter

(iv) Succesive approximation A/D converter

(v) Flash ADC

**(i) Digital Ramp A/D Converter**

This method is also known as counter or stair step ramp method because the waveform is a step by step ramp. figure shows the diagram for a digital ramp ADC.

it uses a counter a DAC an analog comparator and a controlled AND gate. the comparator serves as the active low end of conversion signal EOC.

The conversion time is the time interval between the end of start pulse and the activation of the end of conversion output. the maximum conversion time is given by

t_{c (max) } = (2^{n} – 1) x clock cycles and average conversion time is given by

t_{c (av)} = t_{c (max)}/2 = (2^{n} – 1/2) x clock cycles

The disadvatages of this type of converter is its large conversion time.

**(ii) Single Slope A/D Converter**

It consists of a ramp generator and BCD or binary counters. the figure shows the single slope ADC.

The resolution of single slope ADC is less and variation in ramp generator due to time, temperature and voltage sensitiyity also cause a lot of problem.

**(iii) Dual Slope A/D Converter**

Dual slope conversion is an indirect method conversion where an analog voltage and a reference voltage are converted into time period by integrator and then measured by counter. the speed of this conversion is slow but accuracy is high.

Here, t_{2} = V_{I}/V_{R} t_{1}

Digital output = (Counts/second) t_{2}

= (counts/second) . (V_{I}/V_{R}) t_{1}

Conversion time = 2^{N}T + nT

Maximum conversion time = 2^{n+1} . t

conversion time is independent of input voltage

**Advantages**

- it is highly accurate.
- its cost is low
- it is immune to temperature caused variations in R and C.

**Disadvantage**

its speed is low.

**(iv) Succesive Approximation Converter**

This successive approximation technique uses a very efficient code search strategy to complete n-bit conversion in just n-clock periods.

The time period for one analog digital conversion must depend upon both the clock period T and number of bit N. it is given as

T_{C} = NT

Where, T_{C} = Conversion time

T = clock peiod

N = number of bits.

the conversion time is independent of amplitude of analog signal.

**Example 5. **An 8-bit successive approximation type ADC has 4.50 v full scale. the conversion time for V_{A} = 1.5 V is 75 us. what will the conversion time for V_{A} = 2.5 V?

**Sol. **in successive approximation type ADC conversion time is independent of input voltage. so, conversion time remains same 75 us for V_{A} = 2.5 V.

**(v) Flash ADC**

Flash A/D converters are also known as a simultaneeous or parallel comparator ADC. the circuit shows the 3-bit flash A/D converter.

in this circuit fast speed in accomplished by providing 2^{N} – 1 comparators and simultaneously comparing the input signal with unique reference level speeds 1 LSB apart. thus,

number of comparators = 2^{N} – 1

Conversion time = T

**Example 6.** How many comparators are required for constructing 5-bit flash ADC.

**Sol.** number of comparactors required = 2^{n} – 1

= 2^{5} – 1 = 32 – 1 = 31

**Intro Exercise – 5**

- flash ADC is

(a) a serial ADC

(b) a parallel ADC

(c) partly serial and partly parallel

(d) successive approximation ADC

- for a 5-bit ladder D/A converter which has digital input of 10101, the analog value is (assume 0 = 0 v and 1 = + 10 v, R
_{F}= 3R)

(a) -3.32 V

(b) -4.32 V

(c) -6.56 V

(d) -7.48 V

- An n-bit ADC using V
_{R}as refernce voltage has a resolution (in volt) of

(a) V_{R}/2^{N} – 1

(b) V_{R}N

(c) V_{R}/2^{N-1}

(d) 2N x V_{R}

- A 4-bit D/A converter gives an output voltage of 4.5 V for an input code of 1001. the output voltage for an input code of 0110 is

(a) 1.5 v

(b) 2.0 v

(c) 3.0 v

(d) 4.5 v

- number of comparator required to build a 5-bit analog to digital type of converter is

(a) 5

(b) 11

(c) 31

(d) 21

- 8-bit A/D converter, the quantization error is given by (in per cent)

(a) 0.392

(b) 0.521

(c) 0.212

(d) 0.425

- in an 8-bit D/A converter, the reference voltage used is 10 v. what voltage is represented by 10100001 ?

(a) 0.00392 v

(b) 6.314 v

(c) 6.288 v

(d) 0.00391 v

- an 8-bit digital ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with V
_{T}= 6 mv. what will be the digital output to V_{A}= 6 V ?

(a) 10010111

(b) 10011001

(c) 11001010

(d) 10111010

- among the following the slowest ADC (analog to digital converter) is

(a) counting type

(b) integrating type

(c) successive approximation type

(d) parallel comparator (flash type)

- what is the percentage resolution in the output of a 10 bit D/A converter ?

(a) 0.0978%

(b) 0.5%

(c) 0.205%

(d) 0.1%

- for the DAC shown below step size is 0.5 v. if digital input varies from 0 to 5 v. the value of R
_{F}will be

(a) 800

(b) 1000

(c) 750

(d) 900

- a 12-bit (3 digit) DAC that uses the BCD input code has a full scale output of 9.99 v. the value of V
_{OUT}for an input code of 011010010101 is

(a) 4.11 v

(b) 6.95 v

(c) 7.38 v

(d) 7.88 v

- the full scale output of a DAC is 20 mA. if resolution to be less than 50 uA, then required bits are

(a) 8

(b) 9

(c) 10

(d) 11

- the resolution of an 8-bit optical encoder is

(a) 0.7^{0}

(b) 1.4^{0}

(c) 2.8^{0}

(d) 3.6^{0}

- A 5-bit DAC produces V
_{OUT}= 0.2 V for a digital input of 00001. find the value of V_{OUT}for a input of 11110.

(a) 3 v

(b) 12 v

(c) 6 v

(d) 9 v

- for the 4-bit DAC shown in the figure the output voltage V
_{O}is

(a) 10 v

(b) 5 v

(c) 4 v

(d) 8 v

- the advantage of using a dual slope ADC is digital voltmeter is that

(a) its conversion time is small

(b) its accuracy is high

(c) it gives output in BCD format

(d) it does not require a comparator

- which one of the following statements is correct for an 8-bit successive approximation A/D converter ?

(a) the number of clock cycles required for conversion of any analog signal is 4

(b) the number of clock cycles required for conversion of any analog signal is 8

(c) the conversion time depends upon the analog input signal frequency

(d) the clock cycles required for conversion of any analog signal is dependent on signal amplitude

- a 2 digit BCD D/A converter is a weighted resistor type with V
_{R}= 1 V, R = 1 M and R_{F}= 10 K Resolution in per cent will be

(a) 1%

(b) 2%

(c) 0.1%

(d) 0.2%

- a counter type A/D converter contains a 4-bit binary ladder and a counter driven by a MHz clock. its conversion time and rate will be

(a) 8 us, 105 x 10^{3} conversion/s

(b) 4 us, 125 x 10^{3} conversion/s

(c) 8 us, 125 x 10^{3} conversion/s

(d) 4 us, 105 x 10^{3} conversion/s

**Answers with Solutions**

- (b)

flash ADC is also called parallel ADC.

- (c) for a ladder type D/A converter

V_{A} = -R_{F}V_{R}^{N-1}/3R 2^{N I = 0} d_{i}2^{i}

= -3R/3R . 10/2^{5} [d_{0}2^{0} + d_{i}2^{1} + d_{2}2^{2} + d_{3}2^{3} + d_{4}2^{4}]

= -10/2^{5} [(1 x 2^{0}) + (0 x 2^{1}) + (1 x 2^{2}) + (0 x 2^{3}) + (1 x 2^{4})]

= -10 x 21/32

= – 6.56 v

- (a)

for an n-bit ADC its resolution in volt is given by

resolution = V_{8}/2^{N} – 1

- (c)

output voltage of a D/A converter

V_{0} = V_{R}/2^{N} – 1 (1 + 2^{3}) = V_{R}/15 (9)

For 1001, 4.5 = V_{R}/15.(9)

For 0110,

V_{O} = V_{R}/2^{N} – 1 .(2 + 4) = V_{R} / 2^{N}-1 . (6)

= V_{R}/15 . (6)

= 4.5 /9 X 6

= 3.0

- (c)

number of comparators for N-bit flash ADC

= 2^{n} – 1

for 5-bit ADC

N = 5

So, number of comparators = 2^{5} – 1 = 32 – 1 = 31

- (a)

Quantization error

= 1/ 2^{n }– 1 x 100

= – 1/2^{8} – 1 x 100 = 1/256 – 1 x 100

= 100/255 = 0.3921%

- (b)

voltage represented by 10100001

V_{0} = V_{R}/2^{N} – 1 (1 + 32 + 128

= 10/2^{8} – 1 (161) = 1610/255 = 6.314 V

- (a)

for digital ramp ADC

(Digital output) x (resolution) > V_{A} + V_{T}

(Digital output) x 40 > 6 > 6

Digital output > 6.006/40 x 10^{-3}

Digital output > 150.15

Digital output= 151_{10}

(151)_{10} = (10010111)_{2}

- (b)

Integrating type ADC is the slowest ADC.

- (a)

Percentage resolution

= 1/2^{n} – 1 x 100

= 1/2^{10} – 1 x 100

= 1/1023 x 100

= 0.0978%

- (a)

step size = R_{F}/8K x 5

0.5 = R_{F}/8K x 5

R_{F} = 800

- (b)

step size = 9.99 /999 = 10 mV

(011010010101)_{BCD} = (695)_{10}

So, the output will be

V_{O} = 695 x 10 x 10^{-3}

= 6.95 V

- (b)

I_{FS} = 20 mA, Resolution < 50 uA

Resolution = I_{FS}/2^{N}-1 < 50 uA

20 mA/2^{N} – 1 < 50 uA

2^{N} – 1 > 20 x 1000/50

2^{n} – 1 > 400

2^{n} > 401

N = 9

- (b)

Resolution of an N-bit optical encoder

= 360^{o}/2^{n} -1

for 8-bit optical encoder

resolution = 360^{0}/2^{8} – 1 = 360^{0}/255

Resolution = 1.4^{0}

- (c)

for didital input 00001

V_{0} = V_{R}/2^{N} – 1 . (1)

0.2 = V_{R}/2^{N} – 1

For digital input 11110

V_{O} = V_{R}/2^{N} – 1 . (2 + 4 + 8 + 16)

= V_{R}/2^{N} – 1 . 30

= 0.2 x 30

= 6 V

- (b)

V_{IN} at non-inverting terminal = 1/8 + 1/2 = 5/8

V_{A} = (1 + R_{F}/R) V_{IN}

V_{A} = 8 x 5/8

V_{O} = 5 V

- (b)

it is used because of its high accuracy.

- (b)

for N-bit successive approximation A/D converter N clock cycles are required. so, for 8-bit, 8 clock cycles are required for conversion.

- (a)

percentage reslution for BCD = 1/10^{d} x 100%

where, d is the number of decimal digits.

= 1/10^{2} x 100% = 1%

- (c)

conversion time

= 2^{n}/clock rate = 2^{4}/2 x 10^{6} = 8 us

conversion time

= 1/t_{c} = 1/8 x 10^{-6}

125 x 10^{3 } conversion/s