Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V

By   October 14, 2020

know the answer question Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V ?

Common Data/Linked Answer Questions

Common Data for Questions 1 and 2

Consider the common emitter amplifier shown below with the following circuit parameters :

B = 100, gm = 0.3861 A/V

ro = oo, = 259 k, RS = 1K

RB = 93 K, RC = 250

RL = 1K, C1 = 00 and C2 = 4.7 mF

  1. the resistance seen by the source VS is

(a) 258

(b) 1258

(c) 93 k

(d) infinite

  1. the lower cut-off frequency due to c2 is

(a) 33.9 Hz

(b) 27.1 Hz

(c) 13.6 Hz

(d) 16.9 Hz

Statements for linked answer questions 3 and 4

Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET is increased from zero, while the gate voltage of the p-MOSFET is kept constant at 3 V. assume that for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans conductance parameter and the (W/L) ratio, i.e. the quantity uCox  (W/L) is 1mA/V-2

  1. For small increase in VG beyond 1 V, which of the following gives the correct description of the region of operation of each MOSFET?

(a) both the MOSFETs are in saturation region

(b) both the MOSFETs are in triode region

(c) n-MOSFET is in triode and p-MOSFET is in saturation region

(d) n-MOSFET is in saturation and p-MOSFET is in triode region

  1. Estimate the output voltage VO for VG = 1.5 V.

[Hint Use the appropriate current voltage equation for each MOSFET, based on the answer to question 3]

(a) 4 – 1/2 V

(b) 4 + 1/2 V

(c) 4 – 3/2 V

(d) 4 + 3/2 V

Statements for linked answer questions 5 and 6

In the following transistor circuit VBE = 0.7 V, r = 25 mV/IE and B and all the capacitances are very large.

  1. the value of DC current IE is

(a) 1 mA

(b) 2 mA

(c) 5 mA

(d) 10 mA

  1. the mid- band voltage gain of the amplifier is approximately

(a) – 180

(b) – 120

(c) – 90

(d) – 60

Statements for linked answer questions 7 and 8

Consider the op-amp circuit shown in the figure.

 

  1. the transfer function V0(s) VI (s) is

(a) 1-sRC/1+sRC

(b) 1 + sRC/1 – sRC

(c) 1/1-sRC

(d) 1/1+ sRC

  1. If VI = V1 sin (00t) and VO = V2 sin (00t + 0) then the minimum and maximum values of (in radian) are, respectively

(a) -2/and 2

(b) 0 and 2

(c) – and 0

(d) -2 and 0

Common data for questions 9, 10 and 11

In the transistor amplifier circuit shown in the figure below, the transistor has the following parameters

BDC = 60, VBE = 0.7 V, hw00

the capacitance CC can be assumed to be infinite.

in the figure above, the ground has been shown by the symbol.

  1. Under the DC conditions, the collector to emitter voltage drop is

(a) 4.8 V

(b) 5.3 V

(c) 6.0 V

(d) 6.6 V

  1. If BDC is increased by 10% the collector to emitter voltage drop

(a) increases by less than or equal to 10%

(b) decreases by less than or equal to 10%

(c) increases by more than 10%

(d) decreases by more than 10%

  1. the small-signal gain of the amplifier is

(a) -10

(b) -5.3

(c) 5.3

(d) 10

In the figure above, the ground has been shown by the symbol.

  1. the power dissipation in the transistor Q1 shown in the figure is

(a) 4.8 w

(b) 5.0 w

(c) 5.4 w

(d) 6.0 w

  1. If the unregulated voltage increases by 20%, the power dissipation across the transistor Q1

(a) increases by 20%

(b) increases by 50%

(c) remains unchange

(d) decreases by 20%

Common data for questions 14 and 16

Given, rd = 20 k, IDSS = 10 mA, VP = – 8 V

  1. ZI and ZO of the circuit are, respectively

(a) 2 M and 2 k

(B) 2 M and 20/11 k

(c) infinite and 2 k

(d) infinite and 20/11 k

  1. ID and IDS under DC conditions are, respectively

(a) 5.625 mA and 8.75 V

(b) 7.500 mA and 5.00 V

(c) 4.500 mA and 11.00 V

(d) 6.250 mA and 7.50 V

  1. transconductance in milli-siemen (mS) and voltage gain of the amplifier are, respectively

(a) 1.875 mS and 3.41

(b) 1.875 mS and -3.41

(c) 3.3 mS and -6

(d) 3.3 mS and 6

Statement for linked answer questions 17, 18 and 19

Consider the circuit shown below, assume that diodes are ideal.

  1. If V1 = 10 V and V2 = 5 V, then output voltage VO is

(a) 9 V

(b) 9.474 V

(c) zero

(d) 8.943 V

  1. If V1 = V2 = 10 V, then output voltage VO is

(a) 9 V

(b) 9.474 V

(c) 4 V

(d) 8.943 V

  1. If V1 = – 5 V and V2 = 5 V, then VO is

(a) 9.474 V

(b) 8.943 V

(c)4.5 V

(d) 9 V

Statement for linked answer questions 20 and 21

Consider the circuit shown below. assume diodes are ideal.

  1. If V1 = V2 = 10 V, then output voltage VO is

(a) zero

(b) 9.737 V

(c) 9 V

(d) 9.5 V

  1. If V1 = -5 V and V2 = 10 V, the output voltage VO is

(a) 9 V

(b) 9.737 V

(c) 9.5 V

(d) 4.5 V

Statement for linked answer questions 22 and 24

The diodes in the circuit shown below have linear parameters of VD = 0.6 V and rf = 0.

  1. if V1 = 10 V and V2 = 0 V, then VO is

(a) 8.93 V

(b) 7.82 V

(c) 1.07 V

(d) 2.18 V

  1. If V1 = 10 V and V2 = 5 V, then VO is

(a) 9.13 V

(b) 0.842 V

(c) 5.82 V

(d) 1.07 V

  1. If V1 = V2 = 0, then output voltage VO is

(a) 0.964 V

(b) 1.07 V

(c) 10 V

(d) 0.842 V

Statements for linked answer questions 25 and 26

the diode in the circuit shown below has the non-linear terminal characteristics as shown in figure. let the voltage be VS = cos 00t V.

  1. the current ID is

(a) 2.5 (1 + cos 00t) mA

(b) 5(0.5 + cos oot) mA

(c) 5( 1 + cos 00t) mA

(d) 5(1 + 0.5 cos 00t) mA

  1. the voltage VD is

(a) 0.25(3 + cos 00t) V

(b) 0.25 (1 + 3 cos 00t) V

(c) 0.5 (3 + 1 cos 00t) V

(d) 0.5 (2 + 3 cos 00t) V

Statement for linked answer questions 27 and 29

in the voltage regulator circuit shown below the zener diode current is to be limited to the range 5 < IZ < 100 mA.

  1. the range of possible load current is

(a) 5 < IL < 130 mA

(b) 25 < IL < 120 mA

(c) 10 < IL < 110 mA

(d)none of these

  1. the range of possible load resistance is

(a) 60 < RL < 372

(b) 60 < RL < 200

(c) 40 < RL < 192

(d) 40 < RL < 360

  1. the power rating required for the load resistor is

(a) 576 mW

(b) 360 uW

(c) 480 mW

(d) 75 uW

Statement for linked answer questions 30 to 32

for the transistor in circuit shown below B = 200.

  1. if VB = 0 V, the value of IE and VC are

(a) 6.43 mA, 2.4 V

(b) 2.18 mA, 3.4 V

(c) 0,6 V

(d) none of these

  1. If VB = 1 V, the value of VC is

(a) 4 V

(b) 3 V

(c) 1 V

(d) 1.9 V

  1. if VB = 2 V , the value of VC is

(a) – 7 V

(b) 1.5 V

(c) 2.6 V

(d) none of these

Statement for linked answer questions 33 to 35

the transistor in circuit shown below has B = 200.

  1. If VBB = 0, the value of voltage VO is

(a) 2.46 V

(b) 1.83 V

(c) 3.33 V

(d) 4.04 V

  1. if VBB = 1 V , the value of voltage VO is

(a) 4.11 V

(b) 1.83 V

(c) 2.46 V

(d) 3.44 V

  1. if VBB = 2 V, the value of voltage VO is

(a) 3.18 V

(b) 1.46 V

(c) 0.2 V

(d) none of these

Statement for linked answer questions 36 and 37

Consider the circuit given in figure below, it is given that ISI = 2 IS2 = 5 x 10-16 a.

  1. if I1 = 1.2 mA, the value of VB is

(a) 731.1 mV

(b) zero

(c) 730.6 mV

(d) 1.5 mV

  1. if circuit is at the edge of active region, what is the value of RC ?

(a) 1475 k

(b) 4.95 k

(c) 0.1 k

(d) none of these

Statement for linked answer questions 38 and 39

Consider the transistor amplifier circuit shown below. the transistor parameters are given as B = 100. VBE (on) = 0.7 V. VA = 00

  1. Current gain AI = IO/I1 is

(a) 0.48

(b) 1.00

(c) 0.92

(d) 0.98

  1. Voltage gain AV = VO/VS is

(a) 177.1

(b) 345.2

(c) 50

(d) 384.6

Statement for linked answer questions 40 and 41

in the given darlington pair circuit of figure p 120, transistor Q1 and Q2 parameters are B1r1 and B2r2 respectively.

  1. the current gain AI = IO/I1 of the circuit is

(a) B1B2

(b) B1 + B2

(c) B1 + B2 + B1B2

(d) B1 + B2 – B1B2

  1. input impedance RIN is

(a) r1 + r2

(b) r1 + (1 + B1) r2

(c) B1 r1 + B2 r2

(d) (1 + B1) r1 + r2

Statement for linked answer questions 42 and 43

for the p-channel transistor in the circuit shown below the parameters are IDSS = 6 mA, VP = 4 V and = 0

  1. the value of IDQ is

(a) 8.86 mA

(b) 6.39 mA

(c) 4.32 mA

(d) 1.81 mA

  1. the value of VSD is

(a) -4.28 V

(b) 2.47 V

(c) 4.28 V

(d) 2.19 V

Statement for linked answer questions 44 and 45

for the following circuit transistor parameters are IDSS = 6 mA, VP = – 6 V, B = 100, VBE = 0.7 V.

  1. Voltage VC nearly equals to

(a) 5.67 V

(b) 0.73 V

(c) 1.2 V

(d) 10.93 V

  1. VDS is nearly equal to

(a) 11.42 V

(b) 5.75 V

(c) 0.49 V

(d) 10.2 V

Statement for linked answer questions 46 and 47

An n-channel JFET amplifier circuit is shown in figure.

transistor parameters are given as

IDSS = 12 mA, VP = – 4 V = 0.008 V-1

  1. small-signal transconductance gm is

(a) 9.01 mA /V

(b) 1.5 mA/V

(c) 4.5 mA/V

(d) 2.98 mA/V

  1. small-signal voltage gain AV = VO /VS is

(a) -9.25

(b) -27.72

(c) -4.62

(d) -41.58

Common data/Linked Answer Questions

  1. (b)

the low frequency model

re = 25 mV/IC

= 2.59

the resistance seen by the source

ZIN = RS + (RB||BRE)

= RS + [RB x Bre/RB + Bre

= 103 + (93 x 103 x 100 x 2.59/93 x 103 + (100 x 2.59)

= 103 + 258 – 1258

  1. (b)

the lower cut-off frequency

fl = 1/2 (RL + RC)C2

1/2 (103 + 2.50) (4.7 x 10-6)

1/2 x 1250 x 4.7 x 10-6 = 27.1 Hz

  1. (a)

given, that threshold voltage for p-MOS = 1 V

Gate voltage is 3 V. hence, the p-MOS is in active region.

whereas the threshold voltage for n-MOS = 1 V

When gate voltage VG is increased from 1 V. the n-MOS is in saturation.

  1. (b)
  2. (a) For DC analysis, all capacitors become open circuited. thevenin equivalent of circuit

When, VTH = 10/10 + 20 x 9 V (from voltage divider rule)

= 3 V

and     RTH = 101120 = 10 x 20 /10 + 20 = 6.67 k

As B is very large, IB can be ignored.

Applying KVL in base emitter loop,

VTH – VBE = IERE

IE = VTH – VBE/RE = 1 mA

  1. (d)

the small signal model

gm = |I|/VT = IE/VT = 1mA/25 mV = 1/25 A/V

VO = -gmVin (3k ||3k)

= – 1/25 x Vin x 1.5 k

AV = VO/VIN = – 60

  1. (a)

VA = VI x 1/sC

R + 1/sC

VA = 1/1 + sRC   = VI

From virtual ground concept

VB = VA = 1/ 1 + sRC = Vi

applying KCL at node B,

VI – VB /R1 = VB – VO/R1

Putting the value of VB,

Vo /VI = 1 – sRC/ 1 + sRC

  1. (c)

As       H (S) = VO (s) /VI (s) = 1 – sRC/ 1 + sRC

H (j00) = 1 – j00 RC/ 1 + j00 RC

LH (i00) = – tan -1 00 RC – tan -1 00RC

= – 2 tan-1 00 RC

AT      00  – 00

LH (j00)min

LH (j00) max = 0

  1. (c)

Under DC condition, the circuit becomes

Applying KVL in collector emitter circuit,

12 – 1 k (IC + IB) – VCE = 0

and in base loop.

VCC – 1K (IC + IB) – 5IB – VBE = 0

IC = BIB

Solving eqs. (1), (2) and (3), we get

VCE = 5.95 V.

  1. (b)

As given B increased by 10%.

now, B = 60 + 60 x 10/100 = 66

calculating VCE for B = 66 as in previous question for  B = 60

VCE = 5.69 V

% change = 5.69 – 5.95 /5.95 x 100

= – 4.37%

  1. (a)
  2. (c)

Zener diode is in breakdown, hence

VA = 6 V

V01 = (1 + RF/R1) VA (non-inverting amplifier)

Here,     RF = 12 K , R1 = 24 K

VO1 = 9 V

VCE = 15 – 9 = 6 V

IC = V01/RL = 9/10 = 0.9 A

Power dissipated in Q1

= VCE x IC = 6 x 0.9 = 5.4 W

  1. (b)

As VZ is 6 V.

the V01 and IC will be same.

VOR = 15 + 15 x 20 100 = 18 V

VCE = 18 – 9 = 9 V

PD = VCE x IC = 9 x 0.9 = 8.1 W

% increase = 8.1 – 5.4 /5.4 x 100% = 50%

  1. (b)

the small signal model

ZIN = 2M

ZO = 20 K||20 K = 20/11 K

  1. (a)

VGS = – 2 V < 0, hence FET is operating in active region.

ID = IDSS (1 – VGS/VP)2

= 10 (1 – (-2)/(-8))2 = 5.625 mA

VDS = VDD – IDRD

= 20 – 5.625 x 10-3 x 2 x 103 = 8.75 V

  1. (a)

gm = 2/|VP|ID IDSS = 1.875 mS

A = gm (ra||RD)

= 1.875

  1. (d)

Assume D1 On and D2 off

then, VO = 9/1 + 9 V1 = 9 V

Check assumption

ID1 = V1 – VO/1 = 10 – 9 = 1 mA > 0

Therefore, D1 on

VD2 = V2 – V0

  1. (b)

assume D1 and D2 on,

10/1 + 10 /1

vo = 1/1 + 1/1 + 1/9 = 9.474 V

check assumption

ID1 = ID2 = V1 – VO/1

= 10 – 9.474 /1 = 0.526 > 0

Therefore, D1 and D2 on,

  1. (c)

assume D1 off and D2 on

VO = 9/9 + 1 V2 = 9/9 + 1 (5) = 4.5 V

check asspumption

ID2 = V2 – VO/1 = 5 – 4.5 = 0.5 > 0

therefore, D2 on

VD1 = V1 – VO = – 5 – 4.5 = – 9.5 < 0

Therefore D1 off

  1. (b)

assume D1 and D2 on

10/1 + 10/1 + 5/9

VO = 1/1 + 1/1 + 9/1 = 9.737 V

1 + 1 + 9

  1. (c)

assume D1 off and D2 on,

10/1 + 5/9

VO = 1/1 + 9/1 = 9.5

Check assumption

UD2 = 10 – 9.5 /1 = 0.5 A > 0

Therefore D2 on

VD1 = V1 – VO = -5 – 9.5 = – 1.45 < 0

Therefore D2 off.

  1. (c)

D1 Will be off and D2 Will be on,

10 = 95I + 0.6 + 0.5I

I = 0.94 mA

VO = 10 – 9.5 x 0.94 = 1.07 V

  1. (c)

D1 will be off and D2 will be on.

10 = 9.5i + 0.6 + 0.5i + 5       i = 0.44 mA

VO = 10 – 9.4 i = 5.82 V

  1. (d)

both D1 and D2 will be on and ID1 = ID2 = 1/2

10 = 9.5i +0.6 + 0.5 i/2     i = 0.964 mA

VO = 10 – 0.964 (9.5) = 0.842 V

  1. (c)

the thevenin equivalent circuit for the network to the left of terminal ab is shown below

VTH = 100/200 (2 + cos 00t) = 1 + 0.5 cos 00t V

RTH = (100)2/200 = 50

The diode can be modeled with VF = 0.5 V and

rf = 0.7 – 0.5 /0.004 = 50

ID = VTH  – VF/RTH + rf = 1 + 0.5 cos – 0.5 /50 + 50

= 5 (1 + cos oot) mA

  1. (a)

VD = RFID + VF

= 50 x 5(1 + cos oot) x 10-3 + 0.5

= 0.75 + 0.25 cos oot = 0.25 (3 + cos 00t) V

  1. (b)

current through 12 resistor is

I = 6.3 – 4.8 /12 = 125 mA

IL = I – IZ = 125 – IZ

25 < IL < 120 mA

  1. (c)

25 < IL < 120 mA ILRL = 4.8 V

25 < 4.8/RL < 120 mA

40 < RL < 192

  1. (a)

PL = ILVZ = (120m) (4.8) = 576 mW

 

  1. (c)

VB = 0, transistor is in cut-off region

IE = 0, VC = 6 V

  1. (b)

VB = 1 V. IE = 1- 0.7/1 K = 0.3 mA

IC = IE = 0.3 mA

VC = 6 – ICRC = 6 – (0.3 ) (10) = 3 V

  1. (b)

VB = 2 V, IE = 2 – 0.7/1 = 1.3 mA

IC = IE = 1.3 mA

VC = 6 – (1.3) (10) = – 7 V

Transistor is in saturation. the saturation voltage

VCE = 0.2 V

VE = (1.3) (1) = 1.3 V

VC = VCE + VE = 1.5 V

  1. (c)

VBB = 0, Transistor is in cut -off region

VC = RL /RC + RL VCC = 10 (5) /10 + 5 = 3.33 V

  1. (b)

IB = 1 – 0.7/50K = 6 uA

IC = BIB = 75 x 6u = 0.45 mA

5 – VO/5K = IC + VO/10K

(1 – 0.4) = V0/5 + VO/10

VO = 1.83 V

  1. (c)

IB = 2 – 0.7/50K = 26 uA

IC = BIB  = 75 x 26 uA = 1.95 mA

VC = 5 – ICRC = 5 – 5 x 1.95 = – 4.75 V

Transistor is in saturation,

VCE = 0.2 V = VC = VO

  1. (c)

from the circuit, we get

I1 = IC1 + IC2

IC1 = IS1 evb/v2t,         IC2 = IS2 eve/vt

so, I1 = IS1 eve/vt + IC2 = IS2 eve/vt

= (IS1 + IS2) evb/ve

= (5 x 10-16 + 5/2 x 10-16)evb/vt

As,  IS2 = IS2/2 = 5/2 x 10-16

also, I1 = 1.2 mA

So, 1.2 x 10-3 = 5 x 3/2 x 10-16 evb/26×10-3

VT = 26 x 10-3V

2 x 1.2 x 10-3/15 x 10-16 = evb/26×10-3

2.4 x 1013/15 = evb/26 x 10-3

VB = 26 x 10-3 in (2.4/15 x 1013) = 730.6 mV

  1. (b)

by applying KVL

VCC – ICRC – VC = 0

RC = VCC – VC/I1

As, transistor is at edge of active mode.

so, VS = VC     RC = VCC – VB/I1 = 1475

  1. (d)

by DC analysis of the circuit

IEQ = 10 – 0.7 /(10K) = 0.93 mA

ICQ = (B/B + 1) IEQ = 100 /101 x 0.93 = 0.921 mA

r = BVT/ICQ = (100)(0.026)/0.921 = 2.82 K

gm = ICQ/VT = 0.921/0.026 = 35.42 mA/V

By small signal AC analysis of the circuit

IO = gmV

apply KCL at emitter

I1 = V/T + VS/RE + gmv

I1 = VS/RE||r + gmvs = vs(1/RE||r + gm)

current gain

AI = IO/I1 = gmVs = gm(RE||R) /1 + gm (RE ||r)

= (35.42)(10 k||2.82 k)/1 + (35.42) (10k||2.82 k) = 0.98

  1. (a)

from small signal AC -equivalent circuit

VO  = gmVRC = gmVSRC

AO = VO/VS = gmRC

= (35.42 mA/V)(5 K) = 177.1

  1. (c)

small signal equivalent circuit of the darlington-pair

V1 = I1 R1

So, gm1V1 = gm1 r1i1 = B1i1 …………………(1)

                                                                                 (B1 = gm1 r1)

V2 = (i1 + gm1 v1) r2 = (i1 + B1I1) r2 ………………….(2)

putting V1 and V2 from eqs, (1) and (2)

io = gm1 r1i1 + gm2 (i1 + B1I1) r2

io = B1 i + gm2 (i1 + B1 i1) r2

io = B1 + gm2r2 + gm2 r2 B1

io/i1 = B1 + B2 + B1B2

So,    AI = IO/I1 = B1 + B2 + B1B2

  1. (b)

from equivalent circuit

VS = V1 + V2 = i1r1 + i1 (1 + B1)r2

Rin = VS/F1 = r1 + (1 + B1) r2

  1. (d)

assume transistor is in saturation

VS = – VGS

ID = 0 – VS/RS = VGS/RS = IDSS (1 – VGS/VP)2

RS = 1K

VGS/1 K (6 M) (1 – VGS/4)2

VGS = 8.86, 1.81 V

VGS = 8.86 V is impossible

ID = VGS /RS = 1.81/1K = 1.81 mA

  1. (b)

VD = IDRD – 5 (1.18m) (0.4 k) – 5 = – 4.276 v

VSD = VS – VD = – 1.81 – (-4.276) = 247 V

VSD(SAT) = VP – VGS = 4 – 1.81 = 2.19 V

VSD > VSD(SAT)

Assumption is correct.

  1. (a)

assuming base current is zero,

VB = VG = 10K (16)/(40K + 10K) = 3.2 V

VE = VB – VBE = 3.2 – 0.7 = 2.5 V

IE = VE/RE = 2.5/1.2K = 2.08 mA

IC = IE = 2.08 mA

ID = IC = 2.08 mA

VC = VG – VGS

Where, VGS = VP (1 = ID/IDSS)

VC = (-6) (1 = 2.08/6) = – 2.47 V

VC = 3.2 – (-2.47) = 5.67 V

  1. (b)

from the circuit

VD = 16 – ID (2.2) = 11.42 V

VDS = VD – VS = VD – VC

11.42 – 5.67 = 5.75 V

  1. (d)

By DC analysis of the circuit

VGS = (180/180 + 420) 20 – ID x 2.7

ID = IDSS (1 – VGS/VP)2

So,   VGS = 6 – IDSS (1 – VGS/VP)2 x 2.7

VGS = 6 – (12) (2.7) (1 – VGS/(-4)2

2.025 V2GS = 17.2 VGS + 2.4 = 0

VGS = – 2.01 V

transconductance is

gm = 2IDSS/|VP| (1 – VGS/VP)

= 2 (12) /4 [1 – (2.01)/(-4) ) = 2.98 mA/V

  1. (c)

the small signal equivalent circuit of n-channel JFET is the same as n-channel MOSFET

Here,  R1 = 420 K, R2 = 180 K, RD = 2.7 K

RL = 4 K

Voltage gain

AV = VO/VS = – gm (ro||RD||RL)

Output resistance

ro ~ 1/ID

BY DC analysis

ID = IDSS (1 – VGS/VP)2 = 12 (1 – (-2.01)/(-4))2

= – 2.97 mA

So,   ro ~ 1/ 0.008 x 2.97 = 42.1 k

AV = – 2.98 (42.1||2.7||4) = – 4.62

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