For good stabilized biasing of the transistor of CE amplifier of figure, we should have

By   September 23, 2020

Unit Exercise-2

(2 Marks questions)

  1. Consider the circuit shown in figure below, if the diode used here has the V-I characteristic as in figure below, then the output waveform Vo is
  2. The rms value of a rectangular wave of period T, having a value of + V for a duartion T, (<T) and having -V for the duration, T – T1 = T2 equals

(a) V

(b) T1 – T2/ T  V

(c) V /2

(d) T1/T2 V

  1. For good stabilized biasing of the transistor of CE amplifier of figure, we should have

(a) RE/RB <<1

(b) RE/RB >>1

(c) RB/RE <<1

(d) RB/RE <<1

  1. Discrete transistors T1 and T2 having maximum collector current rating of 0.75 A, are connected in paraller as shown in the figure. this combination is treated as a single transistor to carry a total current of 1 A, when biased with self bias circuit. when the circuit is switched on, T1 draws 0.55 A and T2 draws 0.45 A. if the supply is kept on continuously, ultimately it is very likely that

(a) both T1 and T2 get dmage

(b) both T1 and T2 will be safe

(c) T1 will get damage and T2 will be safe

(d) T2 will get damage and T1 will be safe

  1. The secondary transformer voltage of the rectifier circuit shown below is VS = 60 sin 2 60t V. each diode has a cut-in voltage Vin = 0.6 V the ripple voltage is to be no more than Vrip = 2V. The value of filter capacitor will be

(a) 48.8 uF

(b) 24.4 uF

(c) 32.2 uF

(d) 16.1 uF

  1. The input to full-wave rectifier shown below is VI = 120 sin 2 60t V. The diode cut-in voltage is 0.7 V. if the output voltage cannot drop below 100 V, the required value of the capacitor is

(a) 61.2 uF

(b) 41.2 uF

(c) 20.6 uF

(d) 30.6 uF

  1. For the circuit shown below, diode cut-in voltage is Vin = 0. the ripple voltage is to be no more than VRIP = 4 V. the minimum load resistance, that can be connected to the output is

(a) 6.25 k

(b) 12.50 k

(c) 30 k

(d) none of these

  1. The JFET in the circuit shown in figure below has an IDSS = 10 mA and VP = 5 V. The value of the resistance RS for a drain current IDS = 6.4 mA is

(a) 150

(b) 470

(c) 510

(d) 1 k

  1. In a transistor push-pull amplifier

(a) there is no DC present in the output

(b) there is no distortion in the output

(c) there are no even harmonics in the output

(d) there are no odd harmonics in the output

  1. In a multistage RC copled amplifier, the coupling capacitor

(a) limites the low frequency response

(b) limits the high frequency response

(c) dose not affect the frequency response

(d) blocks the DC component without affecting the frequency of response

  1. Negative feedback in amplifiers

(a) improves the signal to noise ratio at the input

(b) improves the signal to noise ratio at the output

(c) does not affect the signal to noise ration at the output

(d) reduces distortion

  1. The bandwidth of an n stage tuned amplifier with each state having a bandwidth of B, is given by

(a) B/ n

(b) B/n

(c) B  21/n -1

(d) B / 21/N – 1

  1. An n-p-n transistor has a beta cut-off frequency fb of 1 MHz, and common-emitter short circuit low frequency current gain B0 of 200. if unity gain frequency fr and the alpha cut-off frequency fa respectively, are

(a) 200 MHz, 201 MHz

(b) 200 MHZ, 199 MHz,

(c) 199 MHz, 200 MHz

(d) 201 MHz, 200 MHz,

14, The transfer characteristic for the precision rectifier circuit shown below is (assume ideal op-amp and practical diodes)

  1. In the circuit below, the diode is ideal. the voltage V is given by

(a) min (VI,1)

(b) max (VI,1)

(c) min (-Vi,1)

(d) max (-VI,1)

  1. in the following astable multi-vibrator circuit, which properties of Va (t) depend on R2?

(a) only the frequency

(b) only the amplitude

(c) both the amplitude and the frequency

(d) neither the amplitude nor the frequency

  1. A small signal source VI(t) = A cos 20t + B sin 106 t is applied to a transistor amplifier as shown below. the transistor has B = 150 and hie = 3 k which expression best approximates VO (t) ?

(a) VO (t) = – 1500 (A cos 20t + B sin 106 t)

(b) VO (t) = – 150 (A cos 20t + B sin 106 t)

(c) VO (t) = – 1500 B sin 106 t

(d) VO (t) = – 150 B sin 106 t

  1. For the circuit shown in the following figure, transistors M1 and M2 are identical n-MOS transistors. assume that M2 is in saturation and the output is unloaded.

The current IG is related to Iblas as

(a) I= Ibias + IS

(b) Ix  = Ibias

(c) Ix = Ibias – IS

(d) Ix = Ibias – (VCC – VOUT/RE)

  1. The measured transconductance gm of an n- MOS transistor operating in the linear region is plotted against the gate voltage VG at constant drain voltage VD which of the following figures represents the expected dependence of gm on VG?
  2. Consider the following circuit using an ideal op-amp. the I – V, characteristics of the diode is described by the relation I = IO (ev/vt – 1) where VT = 25 mV, IO = 1 uA and V is the voltage across the diode (taken as positive for forward bias)

For an input voltage VI = – 1V, the output voltage VO is

(a) zero

(b) 0.1 v

(c) 0.7 v

(d) 1.1 v

  1. The op-amp circuit shown below represents a

(a) high – pass filter

(b) low-pass filter

(c) band-pass filter

(d) band-reject filter

  1. Two identical n-MOS transistors M1 and M2 are connected as shown below. Vbias is chosen, so that both transistors are in saturation. the equivalent gm of the pair is defined to be IOUT/VI at constant VOUT.

The equivalent gm of the pair is

(a) the sum of individual gm‘s of the transistors

(b) the product of individual gm‘s of the transistors

(c) nearly equal to the gm of M1

(d) nearly equal to gm/go of M2

  1. An astable multi-vibrator circuit using IC 555 timer is shown below in figure, assume that the circuit is oscillating steadily.

The voltage VC across the capacitor varies between

(a) 3 v to 5 v

(b) 3 v to 6 v

(c) 3.6 v to 6 v

(d) 3.6 v to 5 v

  1. Consider the schmitt trigger circuit shown below. A triangular wave which goes from -12 v to 12 v is applied to the inverting input of the op-amp. assume that the output of the op-amp sings from + 15 v to – 15 v. the voltage at the non-inverting input switches between

(a) – 12 v and + 12 v

(b) – 7.5 v and + 7.5 v

(c) – 5 and + 5 v

(d) 0 v and 5 v

  1. For the op-amp circuit shown in the figure below, VO is

(a) – 2 v

(b) -1 v

(c) – 0.5 v

(d) 0.5 v

  1. For the BJT circuit shown in figure below, assume that the B of the transistor is very large and VBE = 0.7. the mode of operation of the BJT is

(a) cut-off

(b) saturation

(c) normal active

(d) reverse active

  1. In the op-amp circuit shown in figure below assume that the diode current follows the equation I = IS exp (V/VT) for VI = 2V, VO = VO1 and for VI = 4 V, VO = VO2. the relationship between VO1 and VO2 is

(a) VO2 = 2 VO1

(b) VO2 E2VO1

(c) VO2 = VO1 in 2

(d) VO1 – VO2 = VT In 2

  1. In the CMOS inverter circuit shown in figure below, if the transconductance parameters of the n-MOS and p-MOS transistors are

Kn = Kp = un Cox Wn/Ln = up Cox Wp /Lp = 40 u/A/V2 and their threshold voltages are VTH,N =|Vth, p| = 1V, the current / is

(a) zero

(b) 25 uA

(c) 45 uA

(d) 90 uA

  1. For the zener diode shown in the figure below, the zener voltage at knee is 7 V, the knee current is negligible and the zener dynamic resistance is 10 if the input voltage (vi) range is from 10 to 16 v, the output voltage (VO) ranges from

(a) 7.00 V to 7.29 V

(b) 7.14 V to 7. 29 V

(c) 7.14 V to 7.43 V

(d) 7.29 V to 7.43 V

  1. For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0, the switch S is closed. the voltage VC across the capacitor a t = 1 ms is

(in the figure shown above, the op-amp is supplied with + 15 V and the ground has been shown by the symbol v).

(a) zero

(b) 6.3 v

(c) 9.45 v

(d) 10 v

  1. For the circuit shown below, assume that the zener diode is ideal with a breakdown voltage of 6 v. the waveform observed across R is
  2. For an n-p-n transistor connected as shown in figure below, Vbe = 0.7 v. given that reverse saturation current of the junction at room temperture 300 k is 10-13 A, the emitter current is

(a) 30 mA

(b) 39 mA

(c) 49 mA

(d) 20 mA

  1. The voltage VO indicated in figure below has been measured by an ideal voltmeter. which of the following can be calculated?

(a) bias current of the invertnig input only

(b) bias current of the inverting and non-inverting inputs

(c) input offset current only

(d) both the bias current and the input offset current

  1. The op-amp circuit shown in figure below is a filter. the type of filter and its cut-off frequency are respectively

(a) high-pass, 1000 rad/s

(b) low-pass, 1000 rad/s

(c) high-pass, 1000 rad/s

(d) low-pass, 1000 rad/s

  1. In an ideal differential amplifer shown in figure below, a large value of RB

(a) increases both the differential and common mode gains

(b) increases the common mode gain only

(c) decreases the differential mode gain only

(d) decreases the common mode gain only

  1. For an n-channel MOSFET and its transfer curve shown in figure below, the threshold voltage is

(a) 1 v and the device is in active region

(b) -1 v and the device is in saturation region

(c) 1 v and the device is in saturation region

(d) – 1 v and the device is in active region

  1. The circuit using a BJT with B = 50 and VBE = 0.7 v shown in figure. the base current Ib and collector voltage Vc are, respectively

(a) 43 uA and 11.4 V

(b) 40 uA and 16 V

(c) 45 uA and 11 V

(d) 50 uA and 10 V

  1. The zener diode in the regulator circuit shown in figure has a zener voltage of 5.8 v and a zener knee current of 0.5 mA. the maximum load current drawn from this circuit ensuring proper functioning over the input voltage range between 20 and 30 v, is

(a) 23.7 mA

(b) 14.2 mA

(c) 13.7 mA

(d) 24.2 mA

  1. Given, the ideal operational amplifier circuit shown in figure indicates the correct transfer characteristics assuming ideal diode with zero cut-in voltage.
  2. The drain of an n-channel MOsfet is shorted to the gate, so that vgs = Vds the threshold voltage (VT) of MOSFET is 1 V. if the drain current (Id) is 1 mA for Vgs = 2 V, then for Vgs = 3 V, ID is

(a) 2 mA

(b) 3 mA

(c) 9 mA

(d) 4 mA

  1. Assuming that the B of the transistor is extremely large and VBE = 0.7 V, IC and VCE in the circuit shown in figure, are

(a) IC = 1 mA, VCE = 4.7 V

(b) IC = 0.5 mA, VCE = 3.75 V

(c) IC = 1 mA , VCE = 2.5 V

(d) IC = 0.5 mA, VCE = 3.9 V

  1. A bipolar transistor is operating in the active region with a collector current of 1 mA. assuming that the B of the transistor is 100 and the thermal voltage (VT) is 25 mV, the transconductance (gm) and the input resistance (ri) of the transistor in the common emitter configuration are

(a) gm = 25 mA/V and ri = 15.625 k

(b) gm = 40 mA/ V and ri = 4.0 k

(c) gm = 25 mA/ V and ri = 2.5 k

(d) gm = 40 mA/ V and ri = 2.5 k

  1. The value of c required for sinusoidal oscillations of frequency 1 kHz in the given circuit, is

(a) 1/2 uF

(b) 2 uF

(c) 1/2 6uF

(d) 2/6 uF

  1. In the op-amp circuit given in figure the load current IL is

(a) – VS/R2

(b) VS/R2

(c) -VS/RL

(d) VS/RL

answer key with solution 

  1. (c) VL < 0.5 V, VO = 0

VL > 0.5 V, VO = 600 /600 + 300 (VL – 0.5)

VO – 2/3 (VL – 0.5)

  1. (a)
  2. (b) For biasing stability R1||R2 = RB

S = RB/RE >>> (B + 1)

S = B + 1

For RB/RE >>> 1, then

S = B + 1 ( 1/B + 1) = 1

Here, RB/RE << 1, So, RE/RB >> 1

  1. (c) T1T2 draw total current = 1 amp

when on, T1 draws 0.55 A

T2 draws 0.45 A

T1 is heated more than T2

Finally, I1 = 1A, I2 = 0

T1 is demaged, T2 safe.

  1. (b) VS = 60 sin 2 60t V

Vmax = 60 – 1.4 = 58.6 V

C = Vmax/2fRVrip = 58.6 / 2(60)10 x 103 x 2 = 24.4 uF

  1. (c) Full wave rectifier

VS = Vt = 120 sin 2 60t V

Vmax = 120 – 0.7 = 119.3 V

Vrip = 119.3 -100 = 19.3 V

C = Vmax/2fkVrip = 119.3 /2(60)2.5 x 103 x 14.4 = 20.6 uF

  1. (a) Vrip = Vmax/fRLC

RL = VMAX/fCVrip = 60 x 50 x 10-5 x 4 = 6.25 k

  1. (a) ID = IDSS [1 – VGS/VP]2

6.4/10 = [1 – VGS/VP]2 = 0.8 – 1 = – VGS/VP

0.2VP = VGS = VGS = 1 V = VGS = IDRS

RS = 1/ 6.4 x 10-3

RS = 156.25

RS = 150

  1. (a,c) In transistor push-pull amplifier, there is no DC present. in output also, there are no even harmonics in output.
  2. (a,d) coupling capacitor limits the low frequency response as well as blocks DC components.
  3. (b,d) Negative feedback improves signal to noise ratio at output and reduces distortion.
  4. (c) Bandwidth of n-stage tuned amplifier with each stage having BW of B is given by

B 21/n – 1

  1. (a) ft = BOFB = 200 x 1 MHz = 200 MHz

fa = fb/1 – a

fa = fb = fb/1 (1 + B) = 1 x 106 x 201

1 – B/1 + B

fa = 201 MHz

  1. (a)

This is an example of control precision. for VI > – 5, diode D2 Conducts and closes the negative feedback loop around the op-amp. a virtual ground therefore will appear at the inverting input termial and the op-amp output will be damped at one diode drop below ground. this negative voltage will keep the diode D1 off, and no current will flow in the feedback resistanece R2 that is, the rectifier output will be zero.

As VI goes negative the voltage at the inverting input terminal will tend to go negative, causing the voltage at the op-amp output terminal to go to positive. this will cause D2 to be reverse biased and bence cut-off. the current through the feedback resistance R2 will be equal to the current through the input resistance R1 For R1 = R2 the output voltage

VO = – VI – 5 for VI < – 5 V

Hence, transfer characteristics will be

  1. (a)

For VI > 1 V, the diode is reverse biased and V = 1 V.

For VI < 1 V, the diode is forward biased and V = VI.

Hence, V = min (VI, 1)

  1. (a)

The output amplitude

VO = R4/R4 + R3(+ Vsat)

the output frequency f = 1/ 2R2C

Hence, only frequency of VO depends on R2

  1. (b)

The output voltage

VO – hfeRC/hie VI

VO – B RC/hie VI

VO – -150 x 3 x 103/3 x 103 VI

VO – 150 VI

VO – 150 (A cos 20 t + B sin 106 t)

  1. (b)

the circuit acts as current mirror.

Ix = (00/L)2 / (00 /L)1 Ibias

since, both the MOSFETs are identical.

(00/L)2 = (00/L)1

Hence, Ix = Ibias

  1. (c)

We know that ID = K (VGS – VT)2

The transconductance

gm = ID/VGS

gm = 2k (VGS – VT)

Hence, gm varies linearly with VGS.

  1. (b)

From virtual ground concept the potential of A, VA = 0. Let the diode conduct, and current flows as indicated in figure.

I = 0 – (-1) /100 K

I = 1 / 100 K

Given,  IO = IO (ev/vt – 1)

1/100 k = 1uA (evo/25 mV -1)

1/ 100 x 103 x 1 x 10-6 = (evo/25 mv – 1)

10 + 1 = 1 = evo/25 mv

VO = 0.1 V

  1. (b)

VO = – Z2/Z1 VI

Z2 = R2 x 1/SC = R2/1 + sR2C

R2 + 1/SC

Z1 = R1 + sL

VO = R2/ (1 + sR2C) (R1 + sL) VI

VO/VI = s2R2LC + s (L + R1R2C) + R1

The standard form of low-pass filter

VO/V1 = K /as2 + bs + c

hence, op-amp circuit represents low-pass filter.

  1. (c)

The equivalent transconductance

gm = gm1gm2/gm2 + gm1

gm2 >> gm1 ; because of Vbias

hence, dgm – gm1

  1. (b)

the capacitor is periodically charged and discharged between 2/3 VCC and 1/3 Vcc.

VC varies between 1/3 x 9 and 2/3 x 9, i.e., between 3 and 6.

  1. (d)

the circuit is let VA be the voltage of non-inverting terminal.

applying KCL at node VA, 1.5 – VA/10 + VO – VA/10 + -15 – VA/ 10 = 0

VA = VO/3

As the output of op-amp swings between – 15V to + 15 v. the voltage between the non-inverting input switches from – 5 to + 5 v.

  1. (c)

VA = 1/1 + 1 (1 V) = 0.5 V (From voltage divided rule)

applying KCL at node B,

1 – VB/1 K = VB – VO/ 2 K

From virtual group concept,

VB = VA = 0.5 V

1 – 0.5 /1 K = 0.5 – VO / 2 K

1 = 0.5 – VO

VO = – 0.5 V

  1. (b)

Assuming BJT is in active region,

IE = 2 – VBE/RE = 2 – 0.7 / 1 K = 1.3 mA

As B is large,

IE = IC = 1.3 mA

Applying KVL in collector emitter loop,

10 – 10IE – VCE – IC = 0

VCE = – 4.3 K

VBC = VBE – VCE

= 0.7 – (- 4.3) = 5 V

Since, VBC > 0.7 V

transistor in saturation.

  1. (d)

VI/R = ID = IS evd/vt

VD = VT IN VI/ISR

Given, when

VI = 2 V

VO = VO1

0 – V01 = VT in 2/ISR ……………..(i)

when VI = 4 V

V0 = V02

0 – V02 = VT in 4/ISR …………….(ii)

subtracting eq. (i) from eq. (ii)

VO2 – VO1 = VT in 4/ISR – VT in 2/ISR

= VT in 4 /ISR x ISR/2 = VT in 2

  1. (d)

Given that

(VT) p -MOS = (VT) n-MOS = 1 v

k = (00/L) p-MOS = (00/L) n-MOS = 40 uA/V2

VGS = 2.5 V

ID = K (VGS – VT)2

= 40 uA/V2 (2.5 – 1)2

ID = 90 uA

  1. (c)

when    VI = 10 V

VR = VI – VZ = 3V

R = 3/200 = 15 mA

V0 = VZ + IR 10 = 7.15 V

When   VI = 10V

VR = 9V

IR = 9/200 = 45 mA

V0 = VZ + 1R x 10 = 7.45 V

Ouput range is 7.15 V – 7.45 V.

  1. (d)

from concept of virtual ground, the potential at 1 is 10 v. appiying KCL at node 1,

0 – 10 /1 k = – c dvc/dt

10 x 10-3 = 1 x 10-6 dvc/dt

VC = 10 x 10-3/1 x 10-6 | dt

= 10 x 10-3/1 x 10-6 x 1 x 10-3 = 10 v

  1. (a)

when 0 < vi < 6V ;

Zener breakdown doesn’t occur and

VR = 0

6V < V1 < 12 V,

VR = VIN – 6

  1. (c)

as collector and base are connected, hence, emitter base junction works as diode.

hence, from diode equation,

ID = IS (ev/nvt – 1)

ID = IE

ID = IS (ev/nvt – 1)

= 10 -13 (e0.7/1 x 26 x 10-3 – 1)

= 49 mA

  1. (c)

The output voltage due to input bias current of inverting terminal is same and the output voltage due to input bias current of non-inverting terminal is same and of opposite sign as resistance is same at both ports.

(VO)offset = IOff R2

hence, by calculating VO, we can measure input offset current only for given circuit.

  1. (a)

let VA be the input of non-inverting input

VO = (1 + RF/R1) VA

VO = (1+1) VA = 2VA

= 2 x V1 x R2 = 2V1R2CS/1 + sR2C

R2 + 1/SC

At DC (low frequency)

VO = 0

At high frequency output is finite hence it is a high-pass filter.

As the pole exits at 1/R2C.

hence, cut-off frequency

00c = 1/R2C = 1/1 x 103 x 1 x 10-6

= 1000 rad/s

  1. (d)

In ideal differential amplifier.

common mode gain = – RC/2RE

Differential mode gain = – gmRC

(doesn’t depend on RE)

Hence, by increasing RE, the common mode gain will be decrease.

  1. (c)

From graph threshold voltage VT = 1V

VDS = VD – VS = 5 – 1 = 4 V

VGS = VG – VS = 3 -1 = 2 V

As    (VDS) > (VGS – VT)

Hence, device is in saturation.

  1. (b)

Applying KVL in collector base circuit,

VCC – IBRB – VBE – IERE = 0

IE = IC + IB

= BIB + IB = IB (1 + B)

VCC – IBRB – VBE – IB (1 + B) RE = 0

IB = VCC – VBE/(1 + B) RE + RB

= 40 uA

IC = BIB = 2 mA

collector voltage VC = VCC – ICRC

= 20 – 2 x 10-3 x 2 x 103

= 16 V

  1. (a)

the maximum current theough load flow when there is maximum input voltage i.e., VIN = 30 V.

Let IE be knee current and IL be load current at Vin = 30 V. Applying KVL,

30 – (IL + IZ) x 1 K – 5.8 = 0

= 24.2 mA

IL = 24.2 mA – IZ

Given,   IZ = 0.5 mA

(IL)max = 24.2 – 0.5

= 23.7 mA

  1. (b)

When VIN < 0; VO > 0,    D2 conducts and D1 does not conduct

VU = 2 K/2.5 K Vsat

= 2 /2.5 x 10 = 8 V

when VIN = 0, VO < 0; D1 conducts and D2 is in cut-off

VI = 2 K /2.5 K Vsat = 2/4 (-10) = – 5 V

  1. (d)

We know that,

IDS = IDSS (1 – VGS/VT)2

1 = IDSS (1 – 2/1)2

IDSS = 1 mA

For     VGS = 3 V

IDS = IDSS(1 – VGS/VT)2 = 1 (1 – 3/1)2 = 4 mA

  1. (c)

Thevenin equivalent of circuit

where,   VTH = 5 x( 1/1 + 4) = 1 V

RTh = 4/5 k

applying KVL in base emitter loop,

VTH – RThIB – VBE = IERE

IE – IC

IC = 1 mA

VCE = 5 – ICRC – IERC = 2.5 V

  1. (d)

Transconductance

gm = |IC| /Vr = 1 mA /25 mV

= 0.04 A /V = 40 mA /V

= B = gmr

= r = B/gm = 100 /40 x 10-3 = 2.5 k

  1. (a)

The given circuit is wien bridge oscillator.

000 = 1/RC

2f0 = 1/RC

C = 1/2f0R = 1/2 x 103 x 103

C = 1/2 uF

  1. (a)

Applying KCL at node A,

VS – VA/R1 = VA – VO/R1

VS – VA = VA – VO

2VA – VO = VA

VA = (VO + VS) /2

Applying KCL at node B,

VB/R2 + IL + VB – VO/R2 = 0

From virtual ground concept,

VA = VB

2 (VO + VS) /2 – VO + ILR2 = 0

IL = – VS/R2

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