mosfet full form | JFET full form meaning in english | FET Amplifiers fet amplifier circuit diagram

By   July 5, 2020

fet amplifier circuit diagram , mosfet full form | JFET full form meaning in english ?

FET Amplifiers

FET  The field effect transistor (FET) is a semiconductor device, which depends for its operation on the control of current by an electric field. As in bipolar transistor circuits, field effect transistors used in anplifier (or other) circuits must be biased into an on-state with constant current and terminal voltage levels.

There are two types of field effect transistors

  1. JFET (Junction field effect transistor)
  2. MOSFET (metal oxide semiconductor field effect transistor)

The FET has several advantages over conventional transistor

  1. In a conventional transistor, the operation depends upon the flow of majoriy and minority carriers. that is why it is called bipolar transistor. in FET, the operation depends upon the flow of majority carriers only. it is called unipolar device.
  2. The input to conventional transistor amplifier involves a forward biased p-n junction with its inherently low dynamic impedance. the input to FET involves a reverse biased p-n junction hence the high input impedance of the order of M.
  3. It is less noisy than a bipolar transistor.
  4. It exhibits no offset voltage at zero drain current.
  5. It has thermal stability.
  6. It is relatively immune to radiation.

The main disadvantage is its relatively small gain bandwidth product in comparison with conventional transistor.

Operation of FET

Consider a sample bar on n-type semiconductor. this is called n-channel and it is electrically equivalent to a resistance as shown in fig. 1(a).

Ohmic contacts are then added on each side of the channel to bring the. external connection. thus, if a voltage is applied across the bar, the current flows through the channel.

The  terminal from where the majority carriers (electrons) enter the channel is channel is called soure designated by S. the terminal through which majority carriers leaves the channel is called drain and designated by D. for an n-channel device, electtrons are the majority carriers. hence, the circuit behaves like a DC voltage. VDS applied across a resistance RDS. The resulting current is the drain current ID. if VDS increases, ID increases proportionally.

Now, on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any method for creating p-n junction. these impurity regions are called gates (gate 1 and gate 2 ) as shown in fig. 1(b).

Both the gates are internally connected and they are grounded yielding zero gate source voltage (VGS = 0 ). The word gate is used because the potential applied between gate and source controls the channel width and hence the current.

As with all p-n junctions,a depletion region is formed on the two sides of the reverse biased p-n junction. the current carriers have diffused across the junction, leaving only uncovered positive ions on the n side and negative ions on the p side. the depletion region width increases with the magnitude of reverse bias. the conductivity of this channel is normally zero because of the unavailability of current carriers.

The potential at any point along the channel depends on the distance of the point from the drain, points close to the drain are at a higher positive potential, relative to ground, then points close to the source. both depletion regions are therefore subjected to greater reverse voltage near the drain. therefore, the depletion region width increases as we move towards drain. the flow of electrons from source to drain is now restricted to the narrow channel between the no conducting depletion regions the width of this channel determines the resistance between drain and source.

Now, consider the behaviour of drain current ID vs drain source voltage VDS. The gate source voltage is zero therefore, VGS = 0. suppose that VDS is gradually linearly increased from 0 V. ID also increases.

Since, the channel behaves as a semiconductor resistance, therefore, it follows ohm’s law. the region is called ohmic region, with increasing current, the ohmic voltage drop between the source and the channel region reverse biased the junction, the conducting portion of the channel begins to constrict and ID begins to level-off until a specific valus of VDS is reached, called the pinch-off voltage VP.

At this point fiurther increase in VDS does not produce corresponding increase in ID Instead, as VDS increases, both depletion regions extend further into the channel, resulting in a no more cross-section, and hence a higher channel resistance. thus even though, there is more voltage, the resistance is also greater and the current remains relatively constant. this is called pinch-off or saturation region. the current in this region is maximum current that FET can produce and designated by IDSS (drain to source current with gate shorted).

As with all p-n junctions, when the reverse voltage exceeds a certain level, avalanche breakdown of p-n junction occurs and ID rises very repidly as shown in fig.1(c)

Now, consider an n-channel JFET with a reverse gate source voltage as shown in fig. 1(d).

The additional reverse bias, pinch-off will occur for smaller values of|vds| and the maximun drain current will be smaller. A family of curves for different values of VGS (negative) is shown in fig. 1(e)

suppose that VGS = 0 and that due of VDS at a specific point along the channel is + 5 v with respect to ground. therefore, reverse voltage across either p-n junction is now 5 v. if VGS is decreased from 0 to -1 v the net reverse bias near the point is 5 – (-1) = 6 v. thus for any fixed value of VDS. the channel width decreases as VGS is made more negative.

Thus, ID value changes correspondingly. when the gate voltage is negative enough, the depletion layers touch each other and the conducting channel pinches-off (disappears). in this case, the drain current is cut-off. the gate voltage that produces cut-off is symbolized GGS (off). it is same as pinch-off voltage.

Since, the gate source junction is reverse biased silicon diode, only a vely small reverse current flow through it. Ideally, gate current is zero. as a result, all the free electrons from the source go to the drain i.e., ID = IS. Because the gate draws almost negligible reverse current. the input resistance is very high 10’s or 100’s of M. therefore, where high input impedance is required JFET is preferred ovre BJT. the disadvantage is less control over output current i.e., FET takes larger changes in input voltage to produce changes in output current. for this reason, JFET has less voltage gain than a bipolar amplifier.

Transconductance Curves

The transconductance curve of a JFET is a graph of output current (ID) vs input voltage (VGS) as shown in fig. 2.

By reading the value of ID and VGS for a particular value of VDS, the transconductance curve can be plotted. the transconductance curve is a part of parabola. it has an equation of data sheet provides only IDSS and VGS (Off) value. using these values the transconductance curve can be plotted.

Biasing FET

The FET can be biased an amplifier. consider the common source drain characteristics of a JFET. For linear amplification, Q point must be selected somewhere in the saturation region. Q point is selected on the basis of AC performance i.e., gain frequency response, noise, power, current and voltage ratings.

Gate Bias

Fig. 3(a) shows a simple gate bias circuit.

Separate VGS supply is used to set up Q point. this is the worst way to select Q point. the reason is that there is considerable variation between the maximum and minimum values of FET parameters e.g.,

IDSS                               VGS (Off)

Minimum                                    4 mA                  – 2 V

Maximum                                  13 mA                  – 8 V

This implies that the minimum and maximum transconductance curves are displaced as shown in fig. 3(b).

Gate bias applies a fixed voltage to the gate. this fixed voltage results in a Q point that is highly sensitive to the particular JFET used. for instance, if VGS = – 1 V the Q point may vary from Q1 to Q2 depending upon the JFET parameter is used.

AT Q1,                    ID = 0.016 {1 – (1/8)}2 = 12.3 mA

AT Q2,                     ID = 0.004 {1 – (1/2)2 = 1 mA

The variation in drain current is very large.

Self Bias

Fig. 4(a) shows a self bias circuit another way to bias a FET. only a drain supply is used and no gate supply. the idea is to use the voltage across RS to produce the gate source reverse voltage.

 

This is a form of a local feedback similar to that used with bipolar transistors. if drain current increases, the voltage drop across RS increases because the IDRS increases. this increases the gate source reverse voltage which makes the channel narrow and reduces the drain current. the overall effect is to partially offset the original increase in drain current. similarly, if ID decreases, drop across RS decreases, hence reverse bias decreases and ID increases.

Since, the gate source junction is reverse biased, negligible gate current flows through RG and so the gate voltage with respect to ground is zero.

VG = 0

The source to ground voltage equals the product of the drain current and the source resistance.

VS = IDRS

The gate sonrce voltage is the difference between the gate voltage and the source voltage.

VGS = VG – VS = 0 – IDRS

VGS = – IDRS

This means that the gate source voltage equals the negative of the voltage across the source resistor. the greater the drain current, the more negative the gate source voltage becomes. Rearranging the equation

ID = – VGS/RS

The graph of this equation is called self bias line and shown in fig. 4(b).

Biasing the Field Effect Transistor

The operating point on transconductance curve is the intersection of self bias line and transconductance curve. the slop of the line is (-1/RS). If the source resistance is very large (-1/RS is small) then Q point is far down the transconductance curve and the drain current is small. when RS  small, the Q point is far up the transconductance curve and the drain current is large. in between there is an optimum value of RS that sets up a Q point near the middle of the transconductance curve.

The tranconductance curve varies widely for FET {because of variation in IDSS and VGS (Off)} as shown in fig. 5(a). the actual curve may be in between their extremes. A and B are the optimum points for the two extremes curves. to find the optimum resistance RS so that Q point is correct for all the curves. A and B points are joined such that it passes through origin.

The slope of this line gives the resistance value RS(VGS = – IDRS). The current IQ is such that IA>IQ>IB. Here, A,Q and B all points are in straight line.

Consider the case where a line drawn to pass between points A and B do not pass through the origin. the equation VGS = – IDRS is not valid. the equation of this line is VGS = VGG – IDRS.

Such a bias relationship may be obtained by adding a fixed bias to the gate in addition to the source self bias as shown in fig. 5(b).

In this circuit,

VGG = RSIG + VGS + IDRS

Since,       RSIG = 0

VGG = VGS + IDRS

Or                VGS = VGG – IDRS

Voltage Divider Bias

The biasing circuit based on single power supply is shown in fig. 6(a). this is similar to the voltage divider bias used with a bipolar transistor.

The Thevenin voltage VTH applied to the gate is

VTH  = R2 / R1 + R2 = VDD

The Thevenin resistance is given as

RTH = R2R1 / R1 + R2

The gate current is assumed to be negligible. VTH is the DC voltage from gate to ground.

VTH = VGS + VS                    (neglecting IG)

VS = VTH = VGS

The drain current ID is given by

ID = VTH – VGS / RS

The DC voltage from the drain to ground is

VD = VDD – IDRD

If VTH is large enough to swamp out VGS the drain current is approximately constant for any JFET as shown in fig. 6(a).

There is a problem in JFET. in a BJT, VBE is approximately 0.7 V,with only minor variations from one transistor to other. in a FET, VGS can vary several volts from one JFET to another. it is therefore, difficult to make VTH large enough to swamp out VGS. for this reason, voltage increases slightly from Q2 to Q1. However, voltage divider bias maintains ID nearly constant.

Consider a voltage divider bias circuit shown in fig. 6(c).

VGS(min) = – 1, VGS(max) = – 5 V

VTh = 15 V

ID(min)   = 15 -(-1) /7.5 = 2.13 mA

ID(max)  = 15 -(-5) /7.5 = 2.67 mA

Difference in   ID(min) and ID(max) is less.

VD(max)  = 30 – 2.13*4.7 = 20

VD(max)  = 30 – 2.67*4.7 = 17.5 V

Current Source Bias

This is another way to produce solid Q point. the aim is to produce a drain current that is independent of VGS. Voltage divider bias and self bias attempt to do this by swamping out of variations in VGS.

Using two power supplies

The current source bias can be used to make ID constant fig 7.

The bipolar transistor is emitter biassed its collector current is given by

ID = (VEE – VBE)/RE

Because the bipolar transistor acts like a current source, it forces the drain current to equal the bipolar collector current.

ID = IC

Since, IC is constant, both Q points have the same value of drain current. the current source effectively wipes out the influence of VGS. Although VGS is different for each Q point, it no longer influences the value of drain current.

Using one power supply

When only a positive supply is available, the circuit shown in fig. 8 can be used to set up a canstant drain current.

In this case, the bipolar transistor is voltage divider biased assuming a stiff voltage divider, the emitter and collector currents are constant for all bipolar transistors. this forces the FET drain current equal the bipolar collector current

VTH = R2VDD / R1 + R2

IE = VTH – VBE / RE

Since, VTH is constant, IE is also constant.

IC = IS = ID = constant

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