programmable array logic definition | what is (PAL) programmable array logic applications question answers mcq devices

By   December 29, 2020

what is (PAL) programmable array logic applications question answers mcq devices definition ?

Programmable Array Logic (PAL)
PAL is a PLD with a fixed OR array and a programmable AND array. because only the AND gates are programmable, the PAL is easier to program but is not as flexible as the PAL. some manufacturers also allow output inversion to be programmed. thus like AND-OR and AND-OR-INVERT logic, they implement a sum of products logic function.
The actual PAL circuits have several groups of AND gates, each group providing inputs to separate OR gates.
It is difficult to show the implementation of PAL in the above connected and disconnected fuse form. for simplifying, if inputs to the OR gates at the outputs are fixed as shown by x marked on the vertical lines. the inputs to the AND gates are marked on the corresponding line by the x removing the x implies blowing-off the corresponding fuse which in tum implies that the corresponding input variable is not applied to the particular AND gate. in this example, the circuit is unprogrammed because all the fusible links are intact.
Note that, the 3-input OR gates in fig. (c) are also drawn with a single input line.
Example 9. Implement the following boolean functions using PAL with four inputs and 3-wide AND-OR structure. Also write the PAL programming table.
F1 (A, B, C, D) = M (2, 12, 13)
F2 (A, B, C, D) = M (7, 8, 9, 10, 11, 12, 13, 14, 15)
F3 (A, B, C, D) = M (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
F4 (A, B, C, D) = M (1, 2, 8, 12, 13)
Sol. The K-maps for the above expressions, their minimization and the minimal expressions obtained from them are shown in figure. note that the function for F4 has four product terms. the logical sum of two of these terms is equal to F1. By using F1 it is possible to reduce the number of terms for F4 from four to three. the implementation of the minimal logic expressions using PAL is shown in figure.
The fuse map for the PAL as specified in the programming table is shown in fig. (a) for each 1 or 0 in the table, we mark the corresponding intersection in the diagram with the symbol for an intact fuse. for each dash, we mark the diagram with blown fuses in both the true and complement inputs. if the AND gate is not used, we leave all its input fuses intact. since, the corresponding input receives both the true and the complement of each input variable, we have AA = 0 and the output of the AND gate is always 0. usually a x inside the AND gate is used to indicate that all its input fuses are intact.
Programmable Logic Array (PLA)
The PAL combines the characteristics of the PROM and the PAL by providing both a programmable OR array and a programmable AND array, i.e., in a PLA both AND gates OR gates have fuses at the inputs. A third set of fuses in the output inverters allows the output function to be inverted, if required.
Like Rom, PLA can be mask programmable or field programmable. with a mask programmable PLA, the user submit a PLA programming table to the manufacturer.
A second type of PLA available is called a field programmable logic array or FPLA. the FPLA can be programmed by the user by means of certain recommended procedures. FPLAs can be programmed with commercially available programmer units.
Example 10. Implement of the following two boolean functions with a PLA
F1 (A, B, C) = M (0, 1, 2, 4)
F2 (A, B, C) = M (0, 5, 6, 7)
Sol. The k-maps for the functions F1 and F2 , their minimization and the minimal expressions for both the true and complement forms of those in sum of products are shown in figure. for finding the minimal in true form, consider the 1’s on the map and for finding the minimal in complement form consider the 0’s on the map.
Considering the 1’s of F1
F1 (T) = AC + BC + AB
Considering the 0’s of F1
F1 = AB + AC + BC
F1 (C) = (AB + AC + BC)
Considering the 1’s of F2
F2 (T) = ABC + AB + AC
Considering the 0’s of F2
F2 = ABC + AB + AC
F2 (C) = ABC + AB + AC
Out of F1 (T), F1 (C), F2 (T), F2 (C), the combination that gives the minimum number of product terms are
F1 (C) = (AB + AC + BC
F 2 (T) = AB + AC + ABC
This gives four distinct terms AB, AC and BC and ABC . the PLA programming table for this combination
Shown in fig. (c). the implementation using a PLA is shown in fig. (d).
F1 is the true output even though a C is marked over it in the table. this is because F1 is generated with an AND-OR circuit and is available at the output of the OR gate. the X-OR gate complements the function to produce the true F1 output.
Programmable ROM (PROM)
PROM is a PLD with fixed AND gates and programmable OR gates. an mxn PROM can be regarded as a PLA having n programmable OR gates, capable of implementing n different logic functions of m variables. A PROM is ideally suited for implementing a logic function directly from a truth table.
Example 11. Realize the following functions using a PROM of size 8 x 3
F1 = M (0, 4, 7)
F2 = M (1, 3, 6)
F3 = M (1, 2, 4, 6)
Sol. An 8 x 3 PROM means a PROM with 8 address lines and 3 outputs. since, the PROM has 8 address lines, we have to use a decoder of size 3 x 8 i.e., a decoder with 3 inputs lines. (number of input lines k is such that 8 = 2k). the number of output functions n = 3. since, the PROM has fixed AND gates no minimization is required. realization of the given functions using an 8 x 3 PROM is shown in figure. the x at the crossover points of the grid indicate the connections. to realize F1 address lines 0, 4 and 7 are connected to the output line F1. To realize F2 address lines 1, 3 and 6 are connected to the output line F2 to realize F3 address lines 1, 2, 4 and 6 are connected to output line F3.
Intro Exercise – 2
1. An n-bit parallel adder consists of
(a) n/2 full adders
(b) 2n half adder
(c) n full adders
(d) (n+1) full adder
2. The boolean function f implemented in the figure using two input multiplexers is
(a) ABC
(b) ABC + ABC
(c) ABC
(d) ABC + ABC
3. Without any additional circuitry, an 8 : 1 MUX can be used to obtain
(a) some but not all boolean functions of 3 variables
(b) All functions of 3 – variables but none of 4-variables
(c) All functions of 3-variables and some but not all of 4 variables
(d) All functions of four variables
4. The logic realized by the circuit shown in figure is
(a) F = A.C
(b) A * C
(c) F = B . C
(d) B * C
5. For the given multiplexer, Y is equal to
(a) ACD + ABC + AD
(b) ABC + ACD + AD
(c) ABC + ACD + AD
(d) ACD + AB
6. Which of the following circuit represents a subractor to subtract A from B?
7. The value of function f (x, y, z) is
(a) II (1,2,4,5,7)
(b) (1,2,4,5,7)
(c) (0,3,6)
(d) None of these
8. Alogical expression in the sum of products (SOP) is suitable for implementation using
(a) AND gates
(b) NOR gates
(c) NAND gates
(d) EX-OR
For the circuit shown for AB = 00, AB = 01, C, S values respectively are :
(a) 0, 0 and 0, 1
(b) 0, 0 and 1, 0
(c) 0, 1 and 0, 0
(d) 1, 0 and 0, 0
10. Two stages of two to furo decoders are shown in figure
The expression for I0′,I1′,I2 and I3′ is :
(a) I0′ = 0 I1 * I2 I2 = I1 I2 I3 = 0
(b) I0 = 1 I1 = I1 I2 = I1 I2 = I3 = 1
(c) I0 = 1 I1 = I1 I2 I2 = I1 I2 I3 = 1
(d) I0 = 0 I1 = I1 I2 I2 = I1 I2 I3 = 0
11. In the circuit shown below, a gray code is converted to :
(a) Exxess-3 code
(b) Binary code
(c) Decimal code
(d) BCD code
12. The network shown in figure implements
(a) NOR gate
(b) NAND gate
(c) XOR gate
(d) XNOR gate
13. f1f2 = ?
(a) x0 x1 x2
(b) x0 * x1 * x2
(c) 1
(d) 0
14. In a full adder denoting sum by S and carry by C
(a) S = 1 when two or more inputs are unity
(b) C = 1 when two or more inputs are unity
(c) C = 1 when all the inputs are unity
(d) S = 1 when all inputs are unity
15. If the number of bits in input and output codes is 4 and 8 respectively for a ROM. the memory of this chip equals to
(a) 12 bits
(b) 32 bits
(c) 128 bits
(d) 256 bits
16. The ‘sum’ output in a half adder can be realized by using a single two input gate which should be a/an
(a) Exclusive OR gate
(b) NOR gate
(c) AND gate
(d) OR gate
17. The logic (s) which is/are not affected by active low or active high level is/are
(a) XOR
(b) NAND
(c) NOR
The correct option is
(a) All of these
(b) (ii) abd (iii)
(c) (i) and (iv)
(d) none of these
18. AN XOR gate with 6 variables is as follows A * B * C * D * E * F. the number of minterms in the boolean expression is
(a) 6
(b) 12
(c) 64
(d) 32
19. With which decoder is it possible to obtain many code conversions?
(a) 2 line to 4 line
(b) 3 line to 8 line
(c) not possible with any decoder
(d) 4 line to 16 line decoder
20. Choose the correct statement (s) from the following
(a) PROM Contains a programmable AND arrey and a fixed OR array
(b) PAL contains a fixed AND array and a programmable OR array
(c) PROM contains a fixed AND array and a programmable OR array
(d) PLA contains a programmable AND array and a pgrogrammable OR array
Answers With Solutions
1. (c)
n-full adders are needed to implement n-bit parallel adder and only 1 full adder is needed to implement serial adder.
2. (a)
F = E. A + E . 0 = E . A
E = BC + BC
F = (BC + BC) A
3. (c)
With the help of 8 : MUX (23 : 1) all functions of 3 variables and some but not all of 4 variables.
4. (d)
F = BC + BC
F = B * C
5. (a)
For the given 8 : 1 MUX
Y = ABCD + ABCD + ABCD + ABC + ABCD + ABC . 0 + ABC D + ABC . 0
(0001) (0011) (0101) (0111) (0110) + ABCD + ABCD (1000) (1100)
Y = AC D + AD + ABC
6. (d)
We have to perform (B – A) operation. hence, the subtraction of two number is carried out by taking the complement of subtrahend and adding it to minuend.
7. (b)
because here output is taken from NOR gate so
f = II (0,3, 6)
f = m 91, 2, 4, 5, 7)
f = (1, 2, 4, 5, 7)
8. (c)
SOP is suitable for implementation using OR gates or NAND gates.
9. (b)
This circuit is half adder and for a half adder
S = A * B
C = A . B
For AB = 00
S = 0 C = 0
For AB = 01
S = 1 C = 1
10. (d)
From the circuit diagram
A1 = I1 * I2
A0 = I1 . I2
A1 A0
0 0 I’0
0 1 I’1
1 0 I’2
1 1 I’3
So, I’0 = A1 . A0 = (I1 . I2) . (I1 . I2) = 0
I’1 = A1 . A0 = (I1 . I2 ) . (I1 . I2)
= (I1 . I2)(I1 . I2)
I’1 = (I1 . I2)
I’2 = A1 . A0 = (I1 . I2) (I1 . I2)
= (I1 . I2 ) (I1 . I2)
I’2 = I1 . I2
I’3 = A1 . A0 = (I1 . I2) (I1 . I2) = 0
I’3 = 0
11. (b)
This circuit represents gray to binary code converter where binary bits are given by
X1 = Y1
X2 = Y1 * Y2
X3 = Y2 * Y3 = ( Y1 * Y2) * Y3
12. (b)
S0 = BC + C . 0 = BC
And f = BC . A + BC
f = A + BC
f = A + B + C
f = ABC
13. (d)
f1 = m (0, 2, 4, 6)
f2 = m (1, 3, 5, 7)
f1f2 = 0
14. (b)
For a full adder circuit
S = A * B * C
C = AB + BC + CA
Thus, the carry will be one when two or more inputs are unity.
15. (c)
Memory of the chip will be = 24 x 8 = 128 bits
16. (a)
Circuit of a half adder
Thus, output of a half adder can be realized by a single exclusive OR gate.
17. (c)
The logic XOR and EQUALITY are not affected by the logics low or high.
18. (d)
The number of minterm for XOR gate with n variable is
= 2n / 2 or 2n-1
so, for n = 6
no, of minterms = 26-1 = 25 = 32
19. (d)
With the help of 4 line to 16 line decoder, it is possible to obtain many code conversions.
20. (c)
PROM contains a fixed AND array and a programmable OR array.

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