operational transconductance amplifier applications , transconductance amplifier formula class 12th ideal characteristics.

**Transconductance **

The transconductance of a FET is defined as

g_{m} = I_{D}/V_{GS} /v_{ds} _{= 0 } uA/V

Because the changes in I_{D} and V_{GS} are equivalent to AC current and voltage. this equation can be written as

The unit of g_{m} is mho or siemens.

Typical value of g_{m} is 2000 mA/V.

The value of g_{m} can be obtained from the transconductance curve as shown in fig. 9(a).

If A and B points are considered, then a change in V_{GS} Produces a change in I_{D}. The ratio of I_{D} and V_{GS} is the value of g_{m} between A and B points. if C and D points are conidered, then same change in V_{gs} produces more change in I_{d}. therefore, g_{m} value is higher. in a natshell, g_{m} tells us how much control gate voltage has over drain current. higher the value of g_{m} the more effective is gate voltage in conrtroling gate current. the second parameter R_{D} is the drain resistance.

R_{D} = V_{DS} / I_{D} /_{VGS} _{= 0 }(R_{D} is negligible)

Similar to bipolar junction transistor, JFET can also be used as an amplifier. the AC equivalent circuit of a JFET is shown in fig 9(b).

The resistance between the gate and the source R_{GS} is very high. the drain of a JFET acts like a current source with a value of g_{m} V_{GS}. This mocel is applicable at low frequencies.

From the AC equivalent model,

I_{D} = g_{m}V_{GS} + V_{DS}/R_{D}

When I_{D} = 0, V_{DS}/V_{GS} = – g_{m}R_{D}

The amplification factor u for FET is defined as

u = V_{DS}/V_{GS} /I_{D = 0 }(u = g_{m}R_{D})

When V_{GS} = 0, g_{m} has its maximum value. the maximum value is designated as g_{mo} . again consider the equation

I_{D} = I_{DSS} [1 – V_{GS} /V_{GS(OFF) }}^{2}

g_{m} = I_{D} / V_{GS} = 21_{DSS} [1 – V_{GS}/V_{GS(OFF)}] [-1 / V_{GS(OFF)}

g_{m} = -2I_{DSS}/V_{GS(OFF)} [1 – V_{GS}/V_{GS(OFF)}]

when V_{GS} = 0, g_{m} = g_{mo} = -2I_{DSS} /V_{GS(OFF)}

g_{m} = g_{mo} [1 – V_{GS} / V_{GS(OFF)}]

As V_{GS} increases, g_{m} decreases linearly.

V_{GS(OFF) }= -2I_{DSS} / g_{m}

Measuring I_{DSS} and g_{m}, V_{GS(OFF) }can be determined.

**FET as Amplifier**

Fig 10(a) shows a common source amplifire.

When a small AC signal is coupled into the gate it produces variations in gate-source voltage. this produces a sinusoidal drain current. since, an AC current flows through the drain resistor. An amplified AC voltage is obtained more drain current, which means that the drain voltage is decreasing. since, the positive half cycle of input voltage produces the negative half cycle of output voltage, we get phase inversion in a CS amplifier.

The AC equivalent circuit is shown in fig. 10(b).

The AC output voltage is

V_{OUT} = – g_{m}V_{GS}R_{D}

Negative sign means phase inversion. because the AC source is directly connected between the gate source terminals therefore AC input voltage equals

V_{In} = V_{GS}

The voltage gain is given by

A_{V} = V_{OUT} / V_{In} = – g_{m}R_{D}

A_{V} = Unloaded voltage gain

The further simplified model of the amplifiers shown in fig. 11(c).

Z_{in} is the input impedance. At low frequencies, there is parallel combination of R_{1}||R_{2}||R_{GS}. since, R_{GS} is very large, it is parallel combination of R_{1} and R_{2}. V_{in} is output voltage and R_{D} is the output impedance.

Because of non-linear transconductance curve, a JFET distorts large signals, as shown in fig. 11(d).

Given a sinusoidal input voltage, we get a non-sinusoidal output current in which positive half cycle is elongated and negative cycle is compressed. this type of distortion is called square law distortion because the transconductance curve is parabolic.

This distortion is undesirable for an amplifier. one way to minimize this is to keep the smill signal. in that case a part of the curve is used and operation is approximately linear. some times swamping resistor is used to minimize distortion and gain constant. now, the source is no longer AC grond as shown in fig. 11(e).

The drain current through r_{s} produdes an AC voltage. between the source and ground. if r_{s} is large enough the local feedback can swamp out the non-linearity of the curve. then the voltage gain approaches an ideal value of R_{D}/r_{s}.

Since, R_{GS} approaches infinity therefore, all the drain current flows through r_{s} producing a voltage drop of g_{m}V_{GS}r_{s}. the AC equivalent circuit is shown in fig. 11(f).

V_{GS} + g_{m}V_{GS}‘r_{s} – V_{in} = 0

V_{in} = (1 + g_{m}r_{s}) V_{GS}

V_{OUT} = – g_{m}R_{D}V_{GS}

A = -g_{m}R_{D} / 1 + g_{m}r_{s} = -R_{D} / r_{s} + 1/g_{m}

The voltage gain reduces but voltage gain is less effective by change in g_{m}‘r_{s} must be greater than 1/g_{m} only then,

V_{GS} = – R_{D} / r_{s}

**Example 1. **Determine g_{m} for an n-channal JFET with characteristic curve shown in figure below.

**sol.** we select an operating region which is approximately in the middle of the curves; that is, between V_{GS } = – 0.8 V and V_{DS} = – 1.2 V, I_{D} = 8.5 mA and I_{D} = 5.5 mA. Therefore, the teansconductance of the JFET is given by

g_{m} = i_{d} / v_{gs} /v_{gs = constant} = 7.5 mho

**Design of JFET Amplifier**

To design a JFET amplifier, the Q point for the DC bias current can be determined graphically. the DC bias current at the Q point should lie between 30% and 70% of I_{DSS}. This locates the Q point in the linear region of the characteristic curves.

The relationship between I_{D} and V_{GS} can be plotted on a dimensionless graph (i.e.,a normalized curve) as shown in fig 12.

The vertical axis of this graph is I_{D }/ I_{DSS} and the horizontal axis is V_{GS} /V_{P}. The slope of the curve is g_{m}.

A reasonable procedure for locating the quiescent point near the centre of the linear operating region is to select I_{DO} ~ I_{DSS} / 2 and V_{GS, Q }~ 0.3 V_{P.} Note that this is near the midpoint of the curye. next we select V_{DS} ~ V_{DD} /2 this gives a wide range of values for V_{DS} that keep the transistor in the pinch-off mode.

The transconductance at Q point can be found from the slope of the curve of fig. 12 and is given by

g_{m} = 1.41 I_{DSS} / V_{P}

**Example 2. **Determine g_{m }for a JFET, where I_{DSS} = 7 mA, V_{P} = – 3.5 V and V_{DD} = 15 V. Choose a reasonable location for the Q point.

**Sol.** Lat us select the Q point as give below

I_{DQ} = I_{DSS}/2 = 3.5 mA

V_{DS} _{Q} = V_{DD}/2 = 7.5 V

V_{GS, Q} = 0.3V_{P} = – 1.05 V

The transconductance g_{m} is found from the slope of the curve at the point I_{D}/I_{DSS} = 0.5 and V_{GS} /V_{P} = 0.3 Hence,

g_{m} = 1.41 I_{DSS}/V_{P} = 2840 umho

**JFET as Analog Switch**

JFET can be used as an analog switch as shown in fig. 13(a). it is the major application of JFET. the idea is to use two points on the load line, cut-off and saturation when JFET is cut-off, it is like an open switch. when it is saturated, it is like a closed switch.

When V_{GS} = 0, the JFET is saturated and operates at the upper end of the load line. when V_{GS} is equal to or more negative than V_{GS}(Off), it is cut-off and operates at lower end of the load line (open and closed switch). this is shown in fig. 13(b).

Only these two points are used for operetion when used as a switch. the JFET is normally saturated well below the knee of the drain curve. for this reason the drain current is much smaller than I_{DSS}.

**FET as a Shunt Switch**

FET can be used as a shunt switch as shown in fig. 14. when V_{con} = 0, the JFT is saturated and the switch is closed. when V_{con} is more negative FET is like an open switch. the equivalent circuit is also shown in fig. 14.

**FET as a Series Switch**

JFET can also be used as series switch as shown in fig. 15. when control is zero, the FET is a closed switch. when V_{con} = negative, the FET is an open switch. it is better than shunt switch.

**Multiplexing**

One of the important application of FET is in analog multiplexer. analog multiplexer is a circuit that selects one of the output lines as shown in fig. 16. when control voltages are more negative, all switches are open and output is zero. when any control voltage becomes zero the input is transmitted to the output.

**Intro Exercise – 3**

- In the circuit shown below the parameters are g
_{m}= 1 mA /V, r_{o}= 50 k. the gain A_{V}= V_{O}/ V_{S}is

(a) – 8.01

(b) 8.01

(c) 14.16

(d) -14.16

- In the given circuit of figure, if V
_{TH}= 0.4 V, the transistor M_{1}is operating in

(a) linear region

(b) satruation region

(c) M_{1} is off

(d) cannot be cletermined

- while biasing JFET, if drain and source are interchanged, then

(a) device will work normally

(b) device will get damaged

(c) device will work but value of I_{D} will get affected

(d) device will not operate at all

- the values of V
_{C}and V_{GS}for the circuit shown in figure are

(a) -2 V, -2 V

(b) 2 V, 2 V

(c) 2 V, -2 V

(d) -2 V, 2 V

- A three stage cascaded amplifier of identical non-interacting FET common source stage has all over an voltage gain of |1000| and overall bandwidth of 25×10
^{6}rad/s.

Given g_{m} = 5 mA /V, the shunt capacitance of each stage is given by

(a) 1.6 pF

(b) 10 pF

(c) 20 pF

(d) 3.2 pF

- Given, for an FET, g
_{m}= 95 mA/V total capacitance is 500 pF. for a voltage gain of – 30, the bandwidth will be

(a) 19 MHz

(b) 6.3 MHz

(c) 100 MHz

(d) 3 MHz

- in the circuit of figure the transistor parameters are as follows:

V_{tp} = – 2 V, K_{P} = 1mA/V^{2} , V_{SG} =?

(a) -3.77 V

(b) 4.37 V

(c) -1.77 V

(d) 1.77 V

- The p-MOS transistor in figure has parameters

V_{TP} = – 1.2 V, w/L = 20

and K_{P} = 30 uA/V^{2}

If I_{D} = 1 mA and V_{D} = – 5 V, then values of R_{S} and R_{D} are

(a) 4 k, 5.8 k

(b) 4 k, 5k

(c) 5.8 k, 4 k

(d) 6.98 k, 5 k

**Statements for linked answer questions 9 and 10**

For the circuit shown below transistor parameters are V_{TN} = 2 V, K_{n} = 0.5 mA/V^{2} and = 0. the transistor is in saturation.

- if I
_{DQ}is to be 0.4 mA, the value of V_{GS,Q}is

(a) 5.14 V

(b) 4.36 V

(c) 2.89 V

(d) 1.83 V

- The value of g
_{m}and r_{o}are

(a) 0.89 mS, infinite

(b) 0.89 mS, zero

(c) 1.48 mS, zero

(d) 1.48 mS, infinite

**Answers with Solutions**

- (a) The small signal equivalent circuit ia as shown below.

V_{GS} = 50 /50+2 v_{s}

V_{a} = g_{m}V_{GS} (50||10) = -50/52 V_{S} (8.33)

A_{V} = V_{O} / V_{S} = – 8.01

- (b) For p-channel MOSFET.

V_{SD} _{(Sat)} = V_{SG} + V_{TH} = (1 – 0) – 0.4 = 0.6

V_{SD} = V_{S} – V_{D} = 1 – 0.3 = 0.7

Here, V_{SD} > V_{SD (Sat)}

So, M_{1} is in saturation region.

- (a) The reversibility of terminals is unique in the case of JFET.
- (a) V
_{GS, Q}= – V_{GG}= – 2 V

V_{GS} = V_{G} – V_{S} = – 2 V

- (b) Gain /stage = 1000 = 10

BW/ stage = 2 x 25 x 10^{6}

C = g_{m} / G (BW)

= 5 x 10^{-3} / 10 x 50 x 10^{6} = 10 pF

- (b) g
_{m}/ c = A_{v}x BW

or 95 x 10^{-3} / 500 x 10^{-12} = 30 x BW

or BW = 6.3 MHz

- (b) R
_{1}= 10 K, R_{2}= 20 K, R_{2}= 1 K, R_{D}= 3 K,

V_{G} = [R_{2} / R_{1} + R_{2}] (30) – 15

= (20 / 10 + 20) (30) – 15

= 5 V

Assume transistor is in saturation.

I_{D} = 15 – V_{S} / R_{S }= K_{P} (V_{SG} + V_{TP})^{2}

15 – V_{S} = R_{S} K_{P} (V_{SG} + V_{TP})^{2}

where V_{S} = V_{G} + V_{SG}

15 – (V_{G} + V_{SG}) = (1 x 10^{3}) (1 x 10^{-3}) (V_{SG} + V_{TP})^{2}

15 – 5 – v_{sg} = (V_{SG} + V_{TP})^{2}

10 – V_{SG} = (V_{SG} + V_{TP})^{2}

10 – V_{SG} = (V_{SG})^{2} + 2V_{SG} – V_{TP} + (V_{TP})^{2}

10 – V_{SG} = (V_{SG})^{2} – 4V_{SG} + 4

(V_{SG})^{2} – 3V_{SG} – 6 = 0

V_{SG} = 4.37 V, – 1.37 V

- (d) K
_{P}= (30 x 10^{-6}/ 2) (20) = 0.3 mA/V^{2}

K_{P} = (K_{P} /2 . w/L)

I_{D} = K_{P} (V_{SG} + V_{TP})^{2}

1 = 0.3 (V_{SG} – 1.2)^{2}

V_{SG} = 3.02 V, V_{G} = 0

V_{S} = V_{SG} = 3.02 V

I_{D} = 10 – V_{S} / R_{S}

R_{S} = 10 – 3.02 / 1 = 6.98 K

I_{D} = V_{D} – (-10) / R_{D}

R_{D} = – 5 + 10 / 1 = 5 K

- (c) I
_{DQ}= K_{N}(V_{GS}– V_{TN})^{2}

0.4 = 0.5 (V_{GS} – 2)^{2}

V_{GD} = 2.89 V

- (a) g
_{m}= 2k_{n}(V_{GS}– V_{TN}) = 2 (0.5) (2.89 – 2)

= 0.89 mA/V = 0.89 mS

r_{o} = (I_{DQ})^{-1, }= 0 r_{o} = _{00}