# ttl with totem pole output | what is ttl circuit with totem-pole output stage minimize gate and advantages disadvantages

By   January 3, 2021

what is ttl circuit with totem-pole output stage minimize gate and advantages disadvantages or ttl with totem pole output ?

TTL with Totem-pole Outout
Figure shows the circuit of a two-input TTL NAND gate with totem-pole output. TTL with active pull-up is known as TTL with totem-pole output.
The operation of the circuit is summarized in table (a)
In terms of 0 and 1, table (a) can be written as in table (b).
Wired-AND Connection
A wired-AND connection has two or more than two gates connected together. using a wired-AND connection, the fan-in of the circuit is increased.
Here, the outputs of two NAND gates are connected together.
Y = Y1 . Y2
Y1 = AB and Y2 = CD
Hence, Y = AB . CD
Using de-morgan’s theoem,
Y = AB + CD
TTL with Open Collector Output
TTL with totem-pole output has a major problem that the two outputs of the two gates cannot be connected together. this problem of TTL with totem-pole output is overcome in TTL with open collector output. figure shows the circuit of a TTL NAND gate with open collector output.
Tri-state TTL
A normal digital circuit has two output states, low and high. the output is either in high state or low state. if the output is not in low state, it should definitely in the high state. the tri-state TTL has three output states, high low and high-impedance.
In TTL with totem-pole output T3 is on when the output is low and T4 is on when the output is high. in high-impedance state, both T3 and T4 in totem-pole arrangement are tured off and as a result the output is open or floating.
When the output is low the driver gate sinks the load current as shown in fig. (a). when the output is high, the driver gate supplies the current to the load as shown in fig. (b). when the output is in high-impedance state, it acts as open or floating and there is no sink and source current as shown in fig. (c).
Tri-state Inverter
The circuit of a tri-state TTL inverter is shown in figure.
The tri-state inverter has two inputs; normal input A and enable input E.
The logic symbols for the active high and actice low enable input inverters are shown in fig. (a) and fig. (b), respectively.
TTL Parameters
Speed of Operation
The speed of operation of a TTL is specified in terms of propagation delay time. for a standard TTL, the propagation delay time is 18.5 ns.
if tPHL = 14 ns and tPHL = 20 ns, then tp = 14 + 20 /2 = 17 ns.
Power Dissipation
It signifies the wastage of power in a digital circuit. it should be as minimum as possible. for a standard TTL, power dissipation 19 mW.
Current and Voltage Parameters
VIH The minimum input voltage to be recognized as logic 1 state.
VIL The maximum input voltage to be recognized as logic 0 state.
VOH The minmum output voltage corresponding to logic 1 state.
VOL The maximum output voltage coresponding to logic 0 state.
For a standard TTL family,
VIH = 2 V, VOH = 2.4 V, VIL = 0.8 V and VOL = 0.4 V
IIH The minimum input current correspondingg to logic 1 state.
IIL The maximum input current corresponding to logic 0 state.
IOH The minimum output current corresponding to logic 1 state. it is called the source current.
IOL The maximum output current corresponding to logic 0 state. it is called the sink current.
for a standard TTL family
IIH = 40 uA and IOH = – 400 uA
IIL = 1.6 mA and IOL = 16 mA
Fan-out
fan-out is nothing but the capacity of the driver gate to drive a number of similar gates.
When the output of the driver gate is low, T3 sinks current from the forward biased emitter junction of transistor of the load as shown in fig. (a). if n similar gates are connected at the output then the total sink current IOL is n times the input current IIL, where n is the fan-out of TTL.
When the output of the driver gate is high, T4 acts as a current source to the load as shown in fig. (b). if n similar gates are connected at the output, then the total source current must be equal to n times the input current IIH, where n is the fan-out of TTL.
IOH = nIIH
n = IOH/IIH = 400/40 = 10
Fan-out = minimum of {IOH/IIH, IOL/IIL}
Fan-out for a standard TTL = Minimum of (10,10) = 10
Noise-Margin
The noise immunity of a digital circuit is its ability tolerate a noise signal. A quantitative measure of noise immunity is known as the noise margin.
Logic 1 level noise margin (1) = VOH – VIH
Logic 0 level noise margin (0) = VIL – VOL
For a standard family,
VIH = 2 V, VOH = 2.4 V, VIL = 0.8 V, VOL = 0.4 V
(1) = 2.4 V – 2 V = 0.4 V
(0) = 0.8 V – 0.4 V = 0.4 V
Improved TTL Series
TTL 54 series/74 series are the most popular and commonly used series of digital ICs. these series have the limitation of speed and power dissipation. these limitations are overcome upto a certain limit in the improved TTL series. the improved TTL seres are as follows :
1. 74L series (low power TTL)
2. 74H series (high speed TTL)
3. 74S series (schottky TTL)
4. 74S series (low-power schottky TTL)
5. 74S series (advanced schottky TTL)
6. 74ALS series (advanced low power schottky TTL)
7. 74F series (fast TTL)
Low Power and High Speed TTL
The 74L series were developed to provide low power dissipation. the 74H series were developed to provide high speed. the 74L series has 1 mW power dissipation and 33 ns propagation delay.
The speed of operation can be increased by reducing the value of the chargning resistor. due to low resistance, the power dissipation is increased. the high speed TTL, 74H series has 6 ns delay and 23 mW power dissipation.
The circuits of 74L series and 74H series are same as the circuit of a standard TTL but they differ in circuit component values.
Schottky TTL
In schottky TTL families, schottky transistors are used instead of normal transistors. the schottky transistor is operated in active region or cut-off region, it never goes into saturation and the storage time delay is negligible.
The schottky transistor is obtained by using a schottky barrier diode between the base and collector terminals of the transistor as shown in fig. (a).
The schottky diode has a forward biased voltage of 0.25 V. because of this diode connected between the base and the collector terminals of the transistor, the collector junction of the transistor cannot get forward biased and the transistor never goes in saturation, the transistor operates in cut-off or active region. the symbol of schottky transistor is shown in fig. (b).
The 74S series is an example of schottky TTL. the propagation delay of schottky TTL is 3 ns. figure shows a basic NAND gate in schottky TTL series.
Low Power Schottky TTL (74LS)
The 74LS series has 9.5 ns propagation delay and 2 mW power dissipation. the 74AS series is an advanced schottky TTL. the 74ALS series is an advanced low power schottky TTL and the 74F series is a fast TTL.
Emitter Coupled Logic
Emitter coupled logic (ECL) is faster than TTL family. the transistors of an emitter coupled logic are operated in cut-off or active region it never goes in saturation therefore, the storage time is eliminated. emitter coupled logic family is an example of unsaturated logic family.figure shows the circuit of an emitter-coupled logic OR/NOR gate.
The circuit consists of difference amplifiers and emitter followers. emitter terminals of the two transistors are connected together hance, it is called as emitter coupled logic.
The emitter followers are used at the output of difference amplifier to shift the DC level. the circuit has two outputs Y1 and Y2 which are complementary. Y1 corresponds to OR logic and Y2 corresponds to NOR logic.
The operation of the circuit is summarized in table (a).
In terms of 0 and 1, table (a) can be written as in table (b).
Wired-OR logic
The ECL circuit has two outputs Y1 and Y2. Y1 is the output of OR logic and Y2 is the output of NOR logic.
(Y1 = A + B, Y2 = Y = A + B). When the outputs of two or more than two gates are connected, then an additional logic is realized without using any additional hardware. consider the circuit shown in figure.
Y4 = Y1 + Y2 = A + B + C + D
Y5 = Y1 + Y2 = A + B + C + D
Consider another circuit shown in figure below
Y4 = Y1 + Y2 = A + B + C + D
Y5 = Y1 + Y2 = A + B + C + D
Unconnected Inputs
If any one of the inputs of the ECL gate is open, then the corresponding transistor operates in cut-off and there is no current flow through the transistor. the same condition occurs when the input is in logic 0 level and hence, the unconnected input of ECL is treated as logic 0.
ECL characteristics
Following are the characteristics of an ECL circuit :
1. less propagation delay time (td = 1 ns.)
2. the logic low level voltage is – 1.7 V and the logic high level voltage is – 8 V.
3. poor noise margin.
4. power dissipation within the range of 40-55 mW.
5. fan-out is 25.
Integrated injection logic (i2l)
The integrated injection logic uses only transistors for the construction of a gate and hence, it becomes, it becomes possible to integrate a large number of gates in a single packag. the figure of merit of I2L circuits is quite small (4 pJ).
(i) I2L Inverter
fig. (a) shows a simple inverter circuit. if the input V1 is at low logic level, transistor T1 is off and IB1 = 0.
The input source acts as a sink for the current supplied by the current source I1 and the output is at high logic level. if the input is high, the base current IB1 = IS + I1 and T1 operates in saturation. the output is at low logic level.
Fig. (b) shows a simple inverter circuit with transistor T2 as the constant current source, hence T2 is in series as a constant current source.
(ii) I2L NAND Gate
figure shows the I2L NAND gate. when inputs A and B are low or any one of the inputs is low, the current provided by T2 is sinked by the source, T1 is off, and the output is high. when both the inputs are high, the base current of T1 is the sum of currents provided by the source and T2, transistor T1 is on and the output is low.
(iii) I2L NOR Gate
Figure shows the I2L NOR gate. the circuit has two inverters with their outputs connected together. when both or any one of the inputs is high, the output of the corresponding inverter is low and the resulting output is low.
When both inputs are low, the output of both the inverters is high and the result is also high.
MOSFET logic
MOSFET’s are very popular due to their low power dissipation and high density of fabrication. the logic families of MOSFETs can be classified into three categories.
(i) p-MOS,
(ii) n-MOS
(iii) CMOS
n-NMOS
MOSFETs are of two types: depletion type and enhancement type. these can further classified as n-channel and p-channel. n-MOS uses only n-channel enhancement MOSFETs.
n-MOS Inverter
In n-MOS inverter consisting of n-channel MOSFETs. when the drain and gate terminals of MOSFETs are short-circuited then it acts as a resistor.
In figure MOSFET Q1 acts as a load resistor and MOSFET Q2 acts as a switching element. Q1 is always on; the load resistance is equal to RON of the n-channel MOSFET. instead of load resistance, Q1 is used, which reduces the size of the chip. Q1 may be of depletion type or enhancement type. but Q2 is always enhancement type.
Operation
When the input signal is high (positive voltage), Q2 is on, the current flows through the drain terminal and the output is low.
When the input signal is low (0 V or negative voltage Q2 is off, there is no current flow through the circuit and the output is high (VDD).
The circuit in figure acts as a NOT gate and its truth table is given in table (a).
n-MOS NAND Gate
Similar to n-MOS inverter Q1 acts as a load resistor that reduces the size of the chip; and here Q1 is always on Q2 and Q3 are the switching elements. these two switching elements are connected in series, which are controlled by the input A and B. Q1 may be of depletion type or enhancement type, but Q2 and Q3 are always enhancement MOSFETs.
Operation
When both of the inputs are low, Q2 and Q3 are off, the current cannot flow through the drain terminal and the output is high (VDD).
When any one of the inputs is low (0 V or negative), then the corresponding MOSFET is off. there is no current flow through the circuit and the output is high (VDD).
When inputs are high (positive voltage) Q2 and Q3 are on. the current flows through the drain terminal and the output is low.
the operation of the circuit is summarized in table (a).
in terms of 0 and 1, table (a) can be written as in table (b).
Propagation Delay Time
It is a function of the capacitor of loaded gate and the charging resistor. in case of MOS devices, the large capacitor is present at input and output and the resistor through which the capacitor gats charged or discharged is also high. hence, the propagation delay is large and the speed of operation is low.
Power Dissipation
It is a function of current supply by the source and resistance of the load. the power supply by the source in MOS logic family is small and hence, the power dissipation is low.
Characteristics of n-MOS
Table summarizes the characteristics of n-MOS.
CMOS
In CMOS, p-channel and n-channel MOS devices are fabricated on the same chip which makes its fabrication complicated but it reduces the packaging density and has small power consumption. hence CMOS is ideally suited for battery-operated systems.
(i) CMOS Inverter
Figure shows a CMOS logic inverter. for the circuit, the logic levels are 0 V and VCC. the p-channel MOSFET is on, when the input is 0 V and the n-channel MOSFET is on, when the input is VCC. Q1 is p-channel and Q2 is n-channel. when Q1 is on, the output voltage is equal to VCC and when Q2 is on, the output voltage is equal 0 V.
Operation
. When the input is low, Q1 is on and Q2 is off, output is high.
. When the input is high, Q1 is off and Q2 is on, output is low.
table shows the operataion of CMOS inverter.
(ii) CMOS NAND Gate
Figure shows a two-inputs CMOS logic NAND gate. it consists of two p-channel and two n-channel MOSFETs. p-channel MOSFETs are connected in parallel and n-channel MOSFETs are connected in sreies. here Q1 and Q2 are p-channel MOSFETs and Q3 and Q4 are n-channel MOSFETs.
Operation
. When the inputs are low Q1 and Q2 are on, Q3 and Q4 are off, and the output is high (VDD).
. When any one of the inputs is low (0 V or negative), then the corresponding MOSFET Q1 or Q2 is on, Q3 or Q4 is on, and the output is high.
. When the inputs are high (positive voltage), Q1 and Q2 are off, Q3 and Q4 are on and the output is low.
the operation of the circuit is summarized in table (a).
CMOS NOR Gate
Figure shows a two-input CMOS logic NOR gate. it consists of two p-channel and two n-channel MOSFETs. n-channel MOSFETs are conneted in parallel and p-channel MOSFETa are connected in series. here, Q1 and Q2 are p-channel. when the input is low, p-channel MOSFETs are on and n-channel MOSFETs are off. when the input is high, p-channel is off and n-channel is on.
Operation
. When inputs are low, Q1 and Q2 are on Q3 and Q4 are off and output is high (VDD).
. When any one of the inputs is low (0 V or negative), then the corresponding MOSFET Q1 or Q2 is on, Q3 or Q4 is on and the output is low.
. When inputs are high (positive voltage), Q1 and Q2 are off Q3 and Q4 are on and the output is low.
Characteristics of CMOS
The 54C/74C series is the commonly used CMOS series of ICs. the electrical characteristics of 54C/74C CMOS logic family are given in table for a supply voltage of 5 V.
Operation Speed
The speed of a logic family is defined in terms of propagation delay. the propagation delay,
tp = tphl + tplh / 2
60 + 45 / 2 = 52.5 ns
Noise Margin
It is the capability of a gate a tolerate noise.
logic 1 level noise margin = VOH – VIH
1 = 4.5 – 3.5 = 1 V
Logic 0 level noise margin = VIL – VOL
0 = 1.5 V – 0.5 V = 1 V
Fan-out
MOS devices have a very high input impedance therefore, the fan-out is large. fan-out of a CMOS is 50 for low frequency and less than 50 for high frequency inputs.
Power dissipation
It is a function of current supply by the source. power dissipation for CMOS logic family is 1 mW at 1 MHz. it is less than 1 mW for frequencies less than 1 MHz.
Unused Inputs
If inputs of unused CMOS gates are open, they are susceptible to noise and static charge that could bias both p and n-channel MOSFETs in the conductive state and power dissipation is increased.
Summary
1. propagation delay
lowest : ECL Logic families
highest : MOS
2. Power dissipation
lowest : CMOS
Highest : ECL
3. Noise margin
lowest : RTL
Highest : CMOS
4. Fan-in capacity
lowest : RTL
Highest : CMOS
5. Fan – out capacity
lowest : RTL
Highest : CMOS
6. Relative cost
lowest : I2 L
Highest : ECL
Intro Exercise – 4
1. which of the following TTL sub-families has maximum speed ?
(a) standard TTL
(b) schottky – clamped TTL
(c) high speed TTL
(d) low power TTL
2. which of the following logics possesses highest noise immunity ?
(a) DTL
(b) HTL
(c) ECL
(d) TTL
3. the figure of merit of a logic family is given by
(a) gain bandwidth product
(b) (propagation delay time) * (power dissipation)
(c) (noise margin) * (power dissipation)
(d) (fan – out) * (propagation delay time)
4. Match list I With list II and select the correct answer using the codes given below the lists.
list 1 list 2
A. TTL 1. Maximum power consumption
B. ECL 2. Highest packing density
C. n-MOS 3. Least power consumption
D. CMOS 4. Saturated logic
5. the circuit shown in given figure is a
(a) positive logic OR circuit
(b) negative logic OR circuit
(c) positive logic NAND circuit
(d) negative logic NAND circuit
6. Which CMOS circuit shown in figure?
(a) positive NAND
(b) negative NAND
(c) positive NOR
(d) negative NOR
7. for the circuit shown in fig. implements the function
(a) (AB + C)D
(b) (A + B) (C + D)
(c) (AB + C) D
(d) (A + B) C + D
8. In the figure shown, points marked 1, 2, 3, 4 are logic-level input voltage ranges for TTL digital ICs. find out the correct combination.
9. if the various logic families are arranged in the descending order of their fan-out capabilities, the sequence will be
(a) TTL, ECL, IIL, CMOS
(b) ECL, TTL, IIL, CMOS
(c) IIL, TTL, ECL, CMOS
(d) CMOS, ECL, TTL, IIL
10. the gate shown in figure is
(a) AND gate
(b) NAND gate
(c) NOT gate
(d) OR gate
11. the ideal inverter in figure shown has a reference voltage of 2.5 v the forward voltage of the diode is 0.75 v. the maximum number of diode logic circuits, that may be cascaded anead of the inverter without producing logic error is
(a) 3
(b) 9
(c) 5
(d) 4
12. the circuit shown in figure is
(a) OR
(b) NOR
(c) NAND
(d) AND
13. the CMOS circuit shown in figure implements
(a) AB + CD + E
(b) (A + B) (C + D)
(c) AB + CD + E
(d) (A + B) (C + D) E
14. the figure shows the internal schematic of a TTL AND-OR invert (AOI) gate. for the inputs shown in the figure, the output Y is
(a) zero
(b) 1
(c) AB
(d) AB
15. both transistors T1 and T2 shown in the figure have a thresold voltage of 1 v. the device parameters K1 and K2 of T1 and T2 are respectively, 36 uA/V2 and 9 uA/V2 . the output voltge VO is
(a) 1 V
(b) 3 V
(c) 2 V
(d) 4 V
16. the typical fan-out of standard TTL is
(a) 6
(b) 14
(c) 12
(d) 10
17. which has the smallest tpd?
(a) TTL standard
(b) ECL
(c) Schottky TTL
(d) CMOS
18. which has the highest fan-out ?
(a) TTL standard
(b) ECL
(c) Schottky TTL
(d) CMOS
19. basic circuit of ECL family is
(a) NOR
(b) XOR
(c) CMOS
(d) NAND
20. if there is unused input, it acts as
(a) logical 0
(b) logical 1
(c) does not affect
(d) none of these
1. (b)
schottky clamped TTL has maximum speed in given sabfamilies.
2. (b)
HTL has the highest noise immunity among all the logic families.
3. (b)
figure of merit for a logic family is defined as figure of merit = (propagation delay time) * (power dissipation)
4. (a)
5. (b)
6. (b)
7. (d)
the operation of the circuit can be given by the truth table as
after solving Y = (A + B) (C + D)
8. (a)
9. (d)
the correct descending order of fan-out is
CMOS > ECL > TTL > ITL
10. (c)
for the given circuit
thus, the circuit will act like a NOT gate.
11. (a)
each diode causes a voltage level loss of 0.75 v.
therefore,
0.75n < 2.5 v
n = 3
12. (d)
if either one or both the inputs are 0 v, the corresponding FET will be off, the voltage across the load FET will be 0 v, hence the output is VDD. if both inputs are VDD, both M1 and M2 are on and the output is V (0) = 0 V. It satisfy NAND gate.
13. (b)
if input E is low output will not be low. it must be high.
14. (a)
for TTL logic floating input = 1
Y = (AB + 1)
= AB . 1 = AB . 0 = 0
15. (b)
ID1 = ID2
K1 (VG1S1 – VT)2 = K2 (VG2S2 – V1)2
36 (5 – V0 – 1)2 = 9 (V0 – 0 – 1)2
V0 = 3 V
16. (d)
fan-out of a TTL is 10.
17. (b)
ECL provides minimum tpd.
18. (a)
TTL standard has the highest fan-out.
19. (a)
basic circuit of ECL family NOR.
20. (b) logical 1.